JPH0245859B2 - HIWATSUSHINKAIRO - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a confidential communication circuit for ensuring confidentiality of telephone calls in wired or wireless communications.

(B) Prior art In normal wireless communication, when Party A and Party B are talking, if third party C receives the carrier frequency range signal used for communication between Party A and Party B, the contents of the call between Party A and Party B can be intercepted. Therefore, there is a problem in that the confidentiality of telephone calls is impaired.

An effective method for ensuring this privacy is to send a scrambled audio signal and restore it on the receiving side. According to this method, a third party who is not equipped with a restoration circuit as a receiver,
Furthermore, since the received voice remains scrambled for a third party with a different key code, the contents of the call cannot be understood, and confidentiality can be maintained.

Balanced modulation type circuit elements are generally commercially available as one type of confidential circuit. This method inverts the frequency spectrum of the audio signal, transmits it, and returns it to the original audio signal upon reception.
Since only about 2 can be obtained, it has the disadvantage that it has no effect on guaranteeing privacy for those equipped with the same type of restoration circuit.

Therefore, the present applicant previously proposed Japanese Patent Application No. 57-164763 entitled ``Secret Communication Method and Apparatus'' dated September 20, 1981. That is, we have proposed a method for compressing and expanding the time axis of an audio signal and transmitting it as a method that has a relatively simple circuit scale and high confidential speech performance. Furthermore, on October 20, 1981, he proposed Patent Application No. 184916 ``Clock circuit for confidential communication system''.
The confidential communication method of the applicant's earlier application can use a large number of key codes.

(c) Purpose The present invention further improves the technology of the prior application and provides a confidential communication circuit that can take a large number of key codes.

(d) Configuration The present invention basically includes a transmitter that scrambles an audio signal, and a receiver that restores the scrambled audio signal. As shown in Figure 1, the basic circuit components include a BBD delay circuit 1 that stores and outputs an input audio signal according to clock pulses, and a voltage controlled oscillator (VCO) that generates the clock pulses. It consists of a generating circuit 2 and a counter circuit 3 for counting the output clock pulses of the clock pulse generating circuit 2. And VCO2
Since the oscillation frequency control voltage of is controlled by the output of the counter circuit 3, the output clock pulse frequency of the VCO 2 is changed accordingly. Furthermore, 4 is
This is a level adjustment circuit for the oscillation control voltage of VCO2.
This basic configuration is the same for both the transmitting section and the receiving section.

The basic operation of the circuit shown in FIG. 1 is to change the frequency of the clock pulse of BBD1 according to the input voltage of VCO2 that supplies the clock pulse.
Scrambled audio is obtained by changing the frequency of the output audio signal of BBD1 with respect to the original one, and on the other hand, in the receiving section, a circuit having the same configuration as the transmitting section By synchronizing with the change in the clock frequency of the BBD1 in the section, the frequency of the received scrambled audio is converted again so as to return to the original frequency, and is restored.

Furthermore, the frequency of the output of VCO 2 is determined according to the oscillation frequency control voltage value of the VCO, and in the present invention, a large number of key codes can be obtained depending on the combination of the output frequencies of the VCO. .

(E) Embodiment An embodiment of the present invention will be described based on FIG.
In the figure, the output of the counter 3 is repeatedly switched between [Hi] and [Lo] every time N clock pulses are counted for the number of delay stages of the BBD 1 (assumed to be 2N). Note that the signal component input to BBD1 is output from BBD1 after N clock pulses have been input (ie, delayed by N clock pulses).

Next, the reason why the number of delay stages of BBD1 is set to 2N will be explained.

In this secret speech circuit, the audio signal input to the variable delay circuit is delayed by N stages (N clocks are input), and then
When output, the frequency of the clock is switched every N clocks. In this case, the audio signal input to the variable delay circuit at frequency f _A is
Therefore _{, the frequency of the audio signal is f B /}
It is output after changing f _A times (see Figure 5).

Here, when a BBD is used as a variable delay circuit, and the number of delay stages of the BBD is k, the audio signal input to the BBD is output after k/2 stages (k/2 clocks are input). The reason is as follows. That is, as shown in FIG. 6, which qualitatively shows the operation, the BBD consists of two delay elements (A) and (B) that form a pair to form one delay element, and the clock (q) When input, the element A ₁ , ₂ ,...
The levels of B ₁ , ₂ , ... become lower, and the elements (A ₁ ) (A ₂ )
Information stored in... (C ₁ ) (C ₂ )... is the element (B ₁ )
(B ₂ ) Move on to... In FIG. 6a, the elements (B ₁ ), (B ₂ ), and (B ₃ ) have no charge. In addition, in FIG. 1B, since the charge is transferred from the element (A) to the element (B), the elements (A ₁ ), (A ₂ ), and (A ₃ ) do not have any charge. Next, clock (Q) (inversion of clock (q))
When input, the element (B ₁ ) is input as shown in C of the same figure.
The level of (B ₂ )... becomes higher, and the information (C ₁ )
(C ₂ )...moves (shifts) to elements (A ₂ ) (A ₃ )...
do. In Figure C, the charge moves from elements (B ₁ ) (B ₂ )... to (A ₂ ) (A ₃ )..., and (B ₁ )
(B ₂ )... has no charge. This situation resembles a bucket brigade. Every time one clock is input here, the information (C) shifts from (Aj) to (Aj+1). Also, Kurotsuku (Q)
Since is the inversion of (q), it is not included in the number of input clocks. In BBD, the number of delay stages is displayed including both elements (A) and (B), so the net number of delays is 1/2 of the number of delay stages.

The information shifting operation inside the BBD is as shown in FIG. 6, and the input/output operation of the BBD is as follows. In other words, the input signal written to the BBD by a clock with a frequency (f _A ) is shifted for each clock input (shifted by two steps in a bucket brigade style as described above), and N = (number of delay stages of BBD/2). ) +1 is input, it is output from the BBD, but since the clock frequency is switched every N clocks, it is output as a clock with frequency (f _B ). Also, an audio signal input using a clock with a frequency of _fB is output at a frequency of _fA .

In this way, in the BBD, two delay elements form a pair to form one delay element. Then, the signal inputted by the first clock to the BBD with the number of delay stages of 2N is shifted by one stage (however, two delay elements are paired) for each clock input.
It is output from BBD at the N+1st clock input.

Figure 2 shows an example of the input and output waveforms of VCO2. The figure shows an example in which the input waveform (oscillation frequency control voltage) of the VCO is rectangular. The voltage values of this waveform are designated as A and B in FIG. 2a, and the output frequencies of the VCO 2 for each voltage value are designated as (f _A ) and (f _B ) as shown in FIG. 2 b.

In this square wave, the time (T ₁ ) is T ₁ =N・
f _A. Then, T ₂ =N·f _B and T = T ₁ +T ₂ . If the clock frequency of BBD1 is f, then BBD
The input signal to is sampled at f and taken into BBD, and after a time delay of t=f・N, the frequency f
is taken out as output from BBD1.

Now, the circuit configuration in Figure 1 (and the circuit configuration in Figure 2)
VCO input/output waveform), for example, the frequency (f _A )
The audio signal sampled at and taken into the BBD is T ₁ = f _A・N, and the clock frequency is f _B
Therefore, this f _B is output from the BBD. In this case, the audio signal extracted from the BBD undergoes time axis conversion, and its frequency changes by a factor of m=f _B /f _A compared to when it was input. Furthermore, the audio signal taken into the BBD at (f _B ) changes by a factor of 1/m=f _A /f _B.

Therefore, the square wave shown in Figure 2 can be applied to the VCO.
, the output audio signal of the BBD is converted into a frequency multiplied by m and 1/m, and becomes a scrambled audio signal.

As an example of this scrambled signal, FIG. 3 shows the case where a sine wave is input to the BBD1.

Next, the case of signal restoration will be explained. The restoring circuit basically operates in the same way as the transmitter scrambling circuit. This will be explained with reference to FIG. In the transmitter, input audio signal (P) to BBD1
is transmitted with a delay of N clocks, but when looking at the entire transmitting/receiving system, it is delayed by 2N clocks,
It is taken out from the receiver BBD. In this case, the audio signal (P) input to the transmitter BBD1 at the frequency (f _A ) has the same clock frequency (f _A ) when taken out from the receiver BBD, so the overall frequency is the same as the original audio frequency. It has been restored. That is, the transmitter
When outputting from the BBD, the frequency is multiplied by m, but in the receiving section, it is multiplied by 1/m, so overall it returns to its original state. In addition, in the above explanation,
The output frequency (f _A ′) (f _B ′) of VCO2 is
It is assumed that f _A ′=f _A and f _B ′=f _B , and that the switching timing of (f _A ′) and (f _B ′) is synchronized with that of the transmitter.

On the other hand, the output frequency of the receiver VCO (f _A ′) (f _B ′)
When is different from the transmitter, the switching times of (f _A ′) and (f _B ′) are different from the transmitter. The reason is that if (T ₁ ) is the sending side and (T ₁ ') is the receiving side, then T ₁ = f _A N,
This is because T ₁ ′=f _A ′N, and the same holds true for (T ₂ ).

Therefore, in this case, for example, the audio signal converted by m=f _B /f _A times in the transmitting section BBD will be converted in the receiving section because the switching times are not synchronized.
Both cases of m'=f _B '/f _A ' or 1/m' frequency conversion can exist. Therefore, the original audio is not completely restored and remains as scrambled audio. This shows that the combination of BBD clock frequencies (VCO output frequencies) can be used as a key code.

According to the experimental results, even when m=m', for example,
It has been confirmed that a sufficient scrambling effect can be obtained by changing f _A ′ by about 1.05 times f _A .
(In the experiment, m=1.5 to 2.0 and fa>f _A ).
According to this result, even when m=m', about 15 key codes can be obtained per octave. or,
You can also create a key code by changing the value of m.
You can also get the key code by exchanging f _A and f _B. Also, the usable range of clock frequencies for BBDs is approximately 10KHz to 100KHz for commercially available BBDs, so 2.5 octaves can be obtained in practice. In this manner, the system of the present invention allows the number of key codes for secret messages to be increased to a practically sufficient number.

Setting the clock frequency when creating a key code can be done by setting the operating point of the VCO2 input voltage, the voltage change range, and the value of the capacitor that determines the time constant that controls the VCO frequency. can.

In addition, in the explanation of the above-mentioned embodiment, for the sake of simplicity,
Frequency (f _A ) (f _B ) every N clock counts
In reality, the period (T) of the input voltage of the VCO is M+N clocks, assuming that the number of delay stages of the BBD on the transmitting side is 2N and the number of delay stages of the BBD on the receiving side is 2M. It suffices as long as it is the time to count.

Next, the reason why the number of delay stages of the BBD on the transmitting side and receiving side is set to 2N and 2M, respectively, will be explained.

The operating principle of the present invention is that if the clock frequency when the signal is output from the BBD is different from that when it is input,
This method takes advantage of the fact that signals are frequency converted, but what is particularly important is that no matter what frequency _a clock is used to output a signal that is input at the transmitting side, there will be a delay at the receiving side. This is based on the fact that if the circuit outputs f _A , it will return to its original state.

When a signal input to the transmitter BBD1 at frequency f _A is output at f _B , the frequency is converted to a=f _B /f _A times.

This signal is input to the receiving side BBD at the same f _B as when outputting from the transmitting side BBD1. The frequency at the time of output is f _C
Then, the original signal will undergo frequency conversion b = (f _B / f _A ) x (f _C / f _B ) in total transmission and reception, but here f _C =
If the condition of f _A is always satisfied, then b=
1, so the signal will be restored.

Therefore, the number of delay stages on the transmitting side and receiving side does not necessarily need to be the same, but it is necessary to make sure that the frequency of the clock at the input of the transmitting side and the clock at the output of the receiving side are the same for the total number of delay stages of transmitting and receiving. In other words, the clock frequency should have periodicity. Assuming that the number of delay stages on the transmitting side is 2N and the number of delay stages on the receiving side is 2M, the signal input to the transmitting side BBD at the kth clock is output from the receiving side BBD at the (k+N+M)th clock. Therefore, the period of the clock can be expressed as the number of clocks (N+N).

In the description of the embodiment, T is the time equivalent to 2N pieces. That is, when the audio signal input to the transmitter BBD1 is sampled at the clock frequency (f), the receiver BBD outputs it with a delay of M+N clocks. If so, overall the audio signal has returned to its original state. Therefore, the switching timing of frequencies (f _A ) (f _B ) does not necessarily have to be N or M, but in experiments, the scrambling effect is greatest when switching every N counts (when M = N). The result is as follows.

(F) Effect As described above, the present invention provides a secret communication circuit that can take a large number of key codes, and if a radio equipped with this system is used, the contents of the call will not be intercepted even if received by a third party. This has a great practical effect in guaranteeing the privacy of calls.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the confidential communication circuit of the present invention.
Figure 2 shows the input and output waveforms of the VCO, Figure 3 shows the scramble signal waveform, and Figure 4 shows the waveforms of the scramble signal.
3 is a drawing showing the basic operation of a BBD delay circuit.
FIG. 5 is a drawing showing write and read pulses of the BBD, and FIG. 6 is a drawing showing how information is shifted inside the BBD. 1...VCO, 2...BBD delay circuit, 3...Counter.

Claims (1)

[Scope of Claims] 1 (a) Signal delay means for sequentially sampling and storing signals in accordance with clock pulses and outputting them; (b) clock pulse generation means for supplying clock pulses for the delay means; (c) A counter means for counting the output clock pulses of the clock pulse generating means is provided on each of the signal transmitting side and the receiving side, and the number of delay stages (2N) of the delay means on the transmitting side and the number of delay stages (2M) of the delay means on the receiving side are provided, respectively. ) sum (2N+
The time period (N+
synchronizing and simultaneously changing the clock frequencies of the clock pulse generating means on the transmitting side and the receiving side at a time corresponding to the number of M clocks (T ₁ +T ₂ );
The time axis of the transmitted signal is alternately compressed and expanded in time before being sent out, and the receiving side synchronizes with the transmitting side and alternately expands and compresses the time axis of the received signal to restore the original signal. Confidential communication circuit to restore. 2. The confidential communication circuit according to claim 1, wherein the clock pulse generating means is a voltage controlled oscillation circuit (VCO). 3 The frequency of the clock pulse supplied to the delay means is set by setting in advance the variation range of the oscillation frequency control voltage of the voltage controlled oscillation circuit, the operating point of the oscillation circuit, or the oscillation time constant of the oscillation circuit, and the frequency of the clock pulse supplied to the delay means is set. 3. The secret communication circuit according to claim 2, wherein the key code is encoded using a combination of frequencies. 4.Claim 3: Two types of clock pulse frequencies are generated by using a rectangular wave as the oscillation frequency control voltage of the voltage controlled oscillation circuit, and the signal is scrambled by repeated switching of the clock pulse frequency and restored on the receiving side. Confidential communication circuit described in section.