JPH0245934A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0245934A JPH0245934A JP19746088A JP19746088A JPH0245934A JP H0245934 A JPH0245934 A JP H0245934A JP 19746088 A JP19746088 A JP 19746088A JP 19746088 A JP19746088 A JP 19746088A JP H0245934 A JPH0245934 A JP H0245934A
- Authority
- JP
- Japan
- Prior art keywords
- contact hole
- wiring
- layer wiring
- tungsten
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 14
- 239000010937 tungsten Substances 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000005530 etching Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 238000001312 dry etching Methods 0.000 abstract description 5
- 238000004544 sputter deposition Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 239000010703 silicon Substances 0.000 abstract description 4
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000009499 grossing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法に関し、特に、多層の配
線を有した半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having multilayer wiring.
従来の技術
従来のＡｌ ２層配線の工程順断面図を第２図に示し、
以下、その工程の説明を行う。尚、簡明化のために、図
中にはＡ１２層配線部のみを示し、あえてトランジスタ
領域の断面は示していない。BACKGROUND TECHNOLOGY Fig. 2 shows a cross-sectional view of a conventional Al two-layer wiring in the order of steps.
The process will be explained below. For the sake of simplicity, only the A12 layer wiring section is shown in the figure, and a cross section of the transistor region is not shown.
まず、第２図ａに示すように、シリコン基板１上に形成
したトランジスタと１層めの配線３とを分離するための
絶縁膜２をＣＶＤ法によシ形成した後、１層めの配線３
（ここでは、Ａｌ膜中に１係のＳＬ原子を含んだＡ１合
金）摸を用いている。）をスパッタリング法により形成
する。続いて、配線として必要な領域のみを残し、他の
領域をエツチング除去する。つきに、１層めの配線３と
２層めの配線７とを電気的に分離するための絶縁膜４を
ＣＶＤ法により形成する。その後、第２図すに示すよう
に、フォトレジスト９のパターンヲ用いて、絶縁膜４に
１層めの１！５！線３と２留めの配線７とを接続するだ
めの孔を形成するため、絶縁膜４を等方向性エツチング
（ここでは弗酸水溶液を用いたエツチングを用いた。）
により、絶、縁膜４の膜厚の３分の１程度エツチングす
る。つづいて、第２図Ｃに示すように、異方性エツチン
グ（ここではプラズマを用いたドライエツチングを用い
た。）によりコンタクトホー／Ｉ１５を形成する。等方
性エツチングと異方性エツチングで並用したため、第２
図Ｃに示すように、コンタクトホール６の上部にテーパ
ーを形成することができる。つぎに、第２図ｄに示すよ
うに、２層めの配線７をスパッタリング法によシ形成す
る。ただし、コンタクトホー ／Ｖ ５の底部の１層め
の配線３の表面には、自然酸化膜であるアルミナ（Ａ１
２０３）が存在するので、Ａｒによりスパッタエツチン
グして、この自然酸化膜を除去した後、連続して２層め
の配線７を形成した。続いて、１層めの配線３の場合と
同様に、配線として必要な領域のみ残し、他はエツチン
グ除去する。最後に、配線で保護するための絶縁膜８を
ＣＶＤ法により形成し、２層配線工程を終了する。First, as shown in FIG. 2a, after forming an insulating film 2 by CVD method to separate the transistor formed on the silicon substrate 1 and the first layer wiring 3, 3
(Here, an A1 alloy containing SL atoms of coefficient 1 in the Al film) is used. ) is formed by sputtering method. Subsequently, only the areas necessary for wiring are left, and the other areas are removed by etching. At the same time, an insulating film 4 for electrically separating the first layer wiring 3 and the second layer wiring 7 is formed by CVD. Thereafter, as shown in FIG. 2, using the pattern of the photoresist 9, the first layer 1!5! In order to form a hole for connecting the wire 3 and the second wiring 7, the insulating film 4 is isodirectionally etched (here, etching using a hydrofluoric acid aqueous solution is used).
As a result, the insulation film 4 is etched to about one third of its thickness. Subsequently, as shown in FIG. 2C, a contact hole /I15 is formed by anisotropic etching (dry etching using plasma was used here). Because isotropic etching and anisotropic etching were used simultaneously, the second
As shown in FIG. C, a taper can be formed in the upper part of the contact hole 6. Next, as shown in FIG. 2d, a second layer of wiring 7 is formed by sputtering. However, the surface of the first layer wiring 3 at the bottom of the contact hole /V 5 is coated with alumina (A1
203), so after removing this natural oxide film by sputter etching with Ar, a second layer of wiring 7 was successively formed. Subsequently, as in the case of the first layer wiring 3, only the area necessary for the wiring is left, and the rest is etched away. Finally, an insulating film 8 for protecting the wiring is formed by the CVD method, and the two-layer wiring process is completed.
発明が解決しようとする課題
しかしながら、上記方法によシ、超ＬＳＩの２層配線で
行った場合、第２図ｄに示すように、コンタクトホー／
Ｉ／６の底部で、２層めの配線のステツブ力パレソジ特
性が悪いため、局所的に膜厚が薄くなっている。そのた
め、配線に電流を流した場合、最も断線（エレクトロマ
イグレーション不良）し易い場所となり、配線の寿命を
短く、信頼性上、好ましくない。また、２層めの配線７
ヒに形成した絶縁膜８のカバレッジ特性も、このコンタ
クトホー）Ｖ５の所で最も悪く、水分等の外部からの侵
入に対し弱くなるため、半導体装置の信頼性上、問題と
なる。Problems to be Solved by the Invention However, when the above method is applied to the two-layer wiring of a VLSI, as shown in FIG.
At the bottom of I/6, the film thickness is locally thin due to poor stabilization properties of the second layer wiring. Therefore, when a current is passed through the wiring, it becomes the place where the wiring is most likely to break (electromigration failure), shortens the life of the wiring, and is unfavorable in terms of reliability. Also, the second layer wiring 7
The coverage characteristics of the insulating film 8 formed on the contact hole V5 are also the worst at the contact hole V5, which is vulnerable to intrusion from the outside such as moisture, which poses a problem in terms of the reliability of the semiconductor device.
課題を解決するだめの手段
１ＦＡめの配線と２層めの配線で接続するコンタクトホ
ールを形成した後、コンタクトホール部にタングステン
を選択的に形成し、コンタクトホーの一部を埋め、この
形成したタングステンをマスクにして、全面のドライエ
ラチングラ行い、コンタクトホールの上部の角を取シ除
き、コンタクトホールにテーパーをつけることにより、
２層めの配線のコンタクトホール部でのカバレッジ特性
の向上を計る。A possible solution to the problem: After forming a contact hole that connects the first FA wiring to the second layer wiring, tungsten was selectively formed in the contact hole to partially fill the contact hole. Using tungsten as a mask, perform dry etching on the entire surface, remove the upper corner of the contact hole, and taper the contact hole.
Measures to improve coverage characteristics in the contact hole part of the second layer wiring.
作 用
本発明は、２層めの配線と１層めの配線との接［−行う
コンタクトホールの底部で、２層めの配線の膜厚が薄く
なることを防ぎ、２層めの配線をコンタクトホール部で
平滑にすることにより、２層めの配線の信頼性を向上さ
せるとともに、２層めの配線上に形成した保護膜のカバ
レッジ特性を良くし、水分等の外部からの浸入を防ぐ。Function The present invention prevents the film thickness of the second layer wiring from becoming thinner at the bottom of the contact hole where the second layer wiring and the first layer wiring connect. By smoothing the contact hole area, it improves the reliability of the second layer wiring, improves the coverage characteristics of the protective film formed on the second layer wiring, and prevents moisture from entering from the outside. .
実施例
本発明にかかるＡｌ ２層配線技術を用いた半導体装置
の製造方法の一実施例を第１図を用いて説明する。Embodiment An embodiment of a method for manufacturing a semiconductor device using the Al two-layer wiring technology according to the present invention will be described with reference to FIG.
尚、簡明化のため、図中にはＡｌ ２層配線部のみを示
し、あえて、トランジスタ領域の断面は省略した。For the sake of simplicity, only the Al two-layer wiring section is shown in the figure, and the cross section of the transistor region is intentionally omitted.
まず、第１図ａに示すように、シリコン基板１上に形成
したトランジスタと１層めの配線３とを分離するために
、厚さ約１μｍの絶縁膜２をＣＶＤ法により形成した後
、厚さ１μｍの１層めの配線３をスパッタリング法によ
り形成する。続いて、配線として必要な領域のみを残し
、他の領域をエツチング除去する。つぎに、１層めの配
線３と２層めの配線７を電気的に分離する絶縁膜４を、
ＣＶＤ法により１．４μｍの厚さで形成する。その後、
第１図すに示すように、絶縁膜４に、１層めの配線３と
２層めの配線７とを接続するためのコンタクトホー／Ｌ
１５で形成する。つぎに、反応ガスＷＦ６とＨ２を用い
、ＣＶＤ法により、タングステン６をコンタクトホール
５に、つまり、１層めの配線３上に選択的に形成し、コ
ンタクトホー／Ｖ６を３分の２程度、タングステン６で
埋める。続いて、第１図Ｃに示すように、タングステン
６をマスクとして用いて、全面をドライエツチングし、
絶縁膜４をエツチングするとともに、コーナ一部でのエ
ツチングレートが大きいことを利用して、コンタクトホ
ー／Ｌ１５の上部の角を削シ取シテーパーを形成する。First, as shown in FIG. 1a, in order to separate the transistor formed on the silicon substrate 1 from the first layer wiring 3, an insulating film 2 with a thickness of about 1 μm is formed by the CVD method. A first layer wiring 3 having a thickness of 1 μm is formed by sputtering. Subsequently, only the areas necessary for wiring are left, and the other areas are removed by etching. Next, an insulating film 4 that electrically isolates the first layer wiring 3 and the second layer wiring 7 is formed.
It is formed with a thickness of 1.4 μm by CVD method. after that,
As shown in FIG.
Formed by 15. Next, using reactive gases WF6 and H2, tungsten 6 is selectively formed in the contact hole 5, that is, on the first layer wiring 3, by the CVD method, and the contact hole /V6 is approximately two-thirds thick. Fill with tungsten 6. Next, as shown in FIG. 1C, the entire surface is dry etched using tungsten 6 as a mask.
While etching the insulating film 4, the upper corner of the contact hole/L15 is etched to form a taper, taking advantage of the fact that the etching rate is high at some corners.
その後、第１図ｄに示すように、厚１μｍの２層めの配
線７をスパッタリング法にて形成する。この場合、コン
タクトホール６の表面がタングステン６のため、自然酸
化膜はほとんど存在しない。それ故、２層めの配線７の
形成前に、Ａｒのスパッタエツチングを行う必要はない
。Thereafter, as shown in FIG. 1d, a second layer of wiring 7 having a thickness of 1 μm is formed by sputtering. In this case, since the surface of the contact hole 6 is tungsten 6, almost no natural oxide film exists. Therefore, it is not necessary to perform Ar sputter etching before forming the second layer wiring 7.
続いて、１層めの配線３の場合と同様に、配線として必
要な領域のみを残し、他はエツチング除去する。最後に
、配線を保護するだめの厚さ１μｍの絶縁膜８をＣＶＤ
法により形成し、２層配線の工程を終了する。Subsequently, as in the case of the first layer wiring 3, only the area necessary for the wiring is left and the rest is removed by etching. Finally, an insulating film 8 with a thickness of 1 μm is deposited by CVD to protect the wiring.
The two-layer wiring process is completed.
尚、同実施例では、Ａ１２層配線工程について説明を行
ったが、本発明は複数の導電層を有する半導体装置全般
において応用できるものである。In the same embodiment, the A12 layer wiring process was explained, but the present invention can be applied to all semiconductor devices having a plurality of conductive layers.
発明の効果
本発明によれば、配線間同志を接続するコンタクトホー
ルを形成した後、コンタクトホー／Ｖｍに選択的にタン
グステンを形成し、続いて、コンタクトホール内に形成
したタングステンをマスクとして用い、全面をドライエ
ツチングすることにより、コンタクトホール上部の角を
取り除き、コンタクトホールにテーパーをつけることが
できる。Effects of the Invention According to the present invention, after forming a contact hole for connecting interconnections, tungsten is selectively formed in the contact hole/Vm, and then the tungsten formed in the contact hole is used as a mask. By dry etching the entire surface, the upper corner of the contact hole can be removed and the contact hole can be tapered.
そのため、コンタクトホール部での上層の配線および保
護膜のカバレッジ特性が向上し、配線の信頼性が大幅に
向上する。Therefore, the coverage characteristics of the upper layer wiring and the protective film in the contact hole portion are improved, and the reliability of the wiring is significantly improved.
第１図は本発明の一実施例における半導体装置の製造工
程を説明するための工程順断面図、第２図は従来の技術
を説明するだめの工程順断面図である。
１・・・・・・シリコン基板、２・・・・・・絶縁膜、
３・・・・・・１層めの配線、４・・・・・・絶縁膜、
６・・・・・・コンタクトホール、６・・・・・・タン
グステン、７・・・・・・２層めの配線、８・・・・・
・絶縁膜、９・・・・・・フォトレジスト。FIG. 1 is a step-by-step sectional view for explaining the manufacturing process of a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a step-by-step sectional view for explaining a conventional technique. 1... Silicon substrate, 2... Insulating film,
3...First layer wiring, 4...Insulating film,
6...Contact hole, 6...Tungsten, 7...2nd layer wiring, 8...
- Insulating film, 9... photoresist.
Claims (1)
する工程と、上記第１の導電層上の上記絶縁膜にコンタ
クト窓を開孔する工程と、化学気相反応により上記コン
タクト窓部に露出した第１の導電層上にタングステンを
形成する工程と、上記タングステンをマスクに上記絶縁
膜の全面エッチングを行い、上記コンタクト窓上部にテ
ーパーを形成することを特徴とする半導体装置の製造方
法。A step of depositing an insulating film on the surface of a semiconductor substrate provided with a first conductive layer, a step of opening a contact window in the insulating film on the first conductive layer, and a step of forming a contact window through a chemical vapor reaction. A semiconductor device comprising the steps of: forming tungsten on a first conductive layer exposed in the window; and etching the entire surface of the insulating film using the tungsten as a mask to form a taper in the upper part of the contact window. Production method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19746088A JPH0245934A (en) | 1988-08-08 | 1988-08-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19746088A JPH0245934A (en) | 1988-08-08 | 1988-08-08 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0245934A true JPH0245934A (en) | 1990-02-15 |
Family
ID=16374871
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19746088A Pending JPH0245934A (en) | 1988-08-08 | 1988-08-08 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0245934A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448658B2 (en) | 2000-06-15 | 2002-09-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having improved interconnection-wiring structures |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181030A (en) * | 1983-03-30 | 1984-10-15 | Toshiba Corp | Manufacture of semiconductor device |
-
1988
- 1988-08-08 JP JP19746088A patent/JPH0245934A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59181030A (en) * | 1983-03-30 | 1984-10-15 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6448658B2 (en) | 2000-06-15 | 2002-09-10 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having improved interconnection-wiring structures |
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