JPH0245960A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH0245960A JPH0245960A JP63196495A JP19649588A JPH0245960A JP H0245960 A JPH0245960 A JP H0245960A JP 63196495 A JP63196495 A JP 63196495A JP 19649588 A JP19649588 A JP 19649588A JP H0245960 A JPH0245960 A JP H0245960A
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- high melting
- wiring
- metal nitride
- alloy
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000002844 melting Methods 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 230000008018 melting Effects 0.000 claims abstract description 22
- 150000004767 nitrides Chemical class 0.000 claims abstract description 18
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 9
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract 3
- 150000004706 metal oxides Chemical class 0.000 claims abstract 3
- 239000010410 layer Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 8
- 125000004430 oxygen atom Chemical group O* 0.000 claims description 5
- 125000004429 atom Chemical group 0.000 claims description 3
- 239000011229 interlayer Substances 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 2
- 239000000956 alloy Substances 0.000 claims description 2
- 239000003870 refractory metal Substances 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 5
- 239000000463 material Substances 0.000 abstract description 3
- 229910052750 molybdenum Inorganic materials 0.000 abstract description 2
- 229910052719 titanium Inorganic materials 0.000 abstract description 2
- 229910052721 tungsten Inorganic materials 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 229910052715 tantalum Inorganic materials 0.000 abstract 1
- 229910052726 zirconium Inorganic materials 0.000 abstract 1
- 238000012421 spiking Methods 0.000 description 7
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000000137 annealing Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001879 gelation Methods 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- WHOPEPSOPUIRQQ-UHFFFAOYSA-N oxoaluminum Chemical compound O1[Al]O[Al]1 WHOPEPSOPUIRQQ-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005546 reactive sputtering Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 101150095744 tin-9.1 gene Proteins 0.000 description 1
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野）
本発明は半導体装置に関する。特に高集積化された高信
頼度な半導体装置に有効である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device. This is particularly effective for highly integrated and highly reliable semiconductor devices.
〔従来の技術１
従来、ＩＣの酉己線購造は、パリアメクルとＡＬの２層
構造が用いられている。例えばＴｉＷやＷバリアメタル
上にＡＬ合金及形成し、８１基板または多結晶シリコン
、シリサイド領域の接続する領域（コンタクトホール領
域）と絶縁膜上の領域は同一構造であった。[Prior art 1] Conventionally, in the case of IC manufacturing, a two-layer structure of a parallel layer and an AL has been used. For example, an AL alloy is formed on TiW or a W barrier metal, and the region (contact hole region) to which the 81 substrate or polycrystalline silicon or silicide region is connected has the same structure as the region on the insulating film.
［発明が解決しようとする課題１
一方配線は、ＡＬの３１基板中へのスパイキング及び表
面ヒロックを回避し、絶縁膜５１０２との密着性を上げ
ることを満足しなければならない。しかしながらＳｉＯ
２との密着性の向上及び３１基板中へのスパイキングの
発生はどちらもバリア金属とＳｉとが反応しやすい場合
に得られるものであり、密着性の向上とスパイキング回
避の両方を満足せず、トレードオフの関係にあった。[Problem to be Solved by the Invention 1] On the other hand, the wiring must satisfy the requirements to avoid spiking into the AL 31 substrate and surface hillocks, and to improve adhesion to the insulating film 5102. However, SiO
Both the improvement in adhesion with 2 and the occurrence of spiking in the substrate 31 are obtained when the barrier metal and Si react easily, and both the improvement in adhesion and the avoidance of spiking can be achieved. There was a trade-off relationship.
また従来の構造では、コンタクト穴がＩａｍ以下になる
とＡＬ配線のステップカバレージが劣化し、空洞が存在
したり、断線したりしてコンタクト穴には上層の高融点
金属の窒化物が形成できずヒロックが発生するという不
具合が多発していた。In addition, in conventional structures, when the contact hole becomes less than Iam, the step coverage of the AL wiring deteriorates, cavities exist, wire breaks occur, and the upper layer of high-melting point metal nitride cannot form in the contact hole, leading to hillocks. There were many problems where this occurred.
本発明はかかる従来の欠申、を回避し、ＡＬスパイキン
グおよび表面ヒロックのない、密着性に優れた、そして
ステップカバレージの良い配線を持つ高信頼性な半導体
装置を提供することを目的とする。It is an object of the present invention to avoid such conventional deficiencies and to provide a highly reliable semiconductor device that is free from AL spiking and surface hillocks, has wiring with excellent adhesion, and has good step coverage. .
［課題を解決するための手段１
本発明では、コンタクト穴領域の配線構造と絶縁物上の
配線構造が異なる。コンタクト穴領域は、Ｔｉ、Ｗ、Ｔ
ａ、Ｍｏ、Ｃｏ、Ｚｒなどの高融点金属シリサイド層と
高融点金属の窒化物、ＡＬ合金及び高融点金属の窒化物
から成り、層間絶縁膜上では、高融１点金属の酸化物及
び高融点金属の窒化物、ＡＬ合金及び高融点金属の窒化
物で構成される。それぞれの高融点金属とそのシリサイ
ド、窒化物は同一の高融点金属である必要はない。すな
わち、例λばＴ ｉ Ｎ ／ Ｔ ｉ、Ｔ ｉ Ｎ／Ｔ
ｉ５ｉｚの構成でも、Ｔ ｉ Ｎ／Ｍｏ、 Ｔ ｉ Ｎ
／ＭＯ３１２の構成でも良い。本発明によれば、コンタ
クト領域では、バリア性が高くかつＡＬ合金及のぬれ性
に優れた材料でＡＬ立直下配線が構成され、絶縁物上で
は、密着性の良い、ぬれ性がコンタクト領よりはやや劣
る材料でＡＬ立直下配線が形成されている。このため、
ＡＬスパイキングが回避でき、密着性が良く、ステップ
カバレージの良い、空洞のない、ＡＬ配線層が形成でき
る。[Means for Solving the Problems 1] In the present invention, the wiring structure in the contact hole region and the wiring structure on the insulator are different. Contact hole area is Ti, W, T
It consists of a silicide layer of a high-melting point metal such as a, Mo, Co, or Zr, a nitride of a high-melting point metal, an AL alloy, and a nitride of a high-melting point metal. It is composed of nitrides of melting point metals, AL alloys, and nitrides of high melting point metals. The respective high melting point metals and their silicides and nitrides do not need to be the same high melting point metal. That is, for example λ, T i N / T i, T i N/T
Even in the i5iz configuration, T i N/Mo, T i N
/MO312 configuration may also be used. According to the present invention, in the contact region, the wiring directly under the AL is made of a material with high barrier properties and excellent wettability with the AL alloy, and on the insulator, the wiring has good adhesion and wettability compared to the contact region. The wiring directly below the AL vertical line is formed of a slightly inferior material. For this reason,
AL spiking can be avoided, and an AL wiring layer with good adhesion, good step coverage, and no cavities can be formed.
このため最上層の高融点金属も均一に形成できＡＬ表面
のヒロックを回避できる。Therefore, the uppermost layer of high melting point metal can also be formed uniformly, and hillocks on the AL surface can be avoided.
〔実 施 例１ 以下実施例を用いて説明する。[Implementation example 1] This will be explained below using examples.
第１．２図は、本発明による半導体の断面図であり、製
造工程をも示している。第１図において８１基板１に形
成された拡散層２と配線層（４，５）は、層間絶縁膜３
で分離され、コンタクトホール１０領域で接続している
。拡散Ｎ２は、ジノサイド層が裏打ちされていても良い
。コンタクトホール１０を形成後、Ｔ１＠４を形成後、
リアクティブ・スパッタによりＴｉＮ層５を形成する。FIG. 1.2 is a cross-sectional view of a semiconductor according to the invention and also shows the manufacturing process. In FIG. 1, the diffusion layer 2 and wiring layers (4, 5) formed on the 81 substrate 1 are connected to the interlayer insulating film 3.
and are connected in the contact hole 10 region. Diffusion N2 may be lined with a dinoside layer. After forming the contact hole 10 and forming T1@4,
A TiN layer 5 is formed by reactive sputtering.
この後、≦１０ｐｐｍＯ２１度のＮ２雰囲気中で６００
°Ｃ〜１１００°Ｃの短時間ランプアニルをすることに
より、コンタクト領域は、第２図に示すようにＴ１シリ
サイド６、ＴｉＮ８に変化する。さらに、コンタクト領
域のＴｉＮには、グレインバウンダリー中にＳｉが拡散
して、Ｓｉを含むＴｉＮ８になっている。またＳｉＯ□
３上のＴｉ層４は、ＳｉＯ□のＯと反応しＴｉ０層１１
と上層はＮ２と反応しＴ ｉ Ｎ４’ に変化する。ま
た極低濃度０２ （≦１０ｐｐｍ）によりＴｉＮ５′の
表面は、弱冠Ｏ原子が侵入している。このあと、２５０
℃以上の加熱スパッタまたはバイアススパッタによりＡ
ＬまたはＡＬ−Ｃｕなどの合金を蓄積する。この時、コ
ンタクト領域のＴｉＮ８に含まれるＳｉ原子は容易にＡ
Ｌに侵入し、ＡＬの融点を下げると同時に、ＡＬのぬれ
性を向上させる。また、ＴｉＮ５’ 、ＴｉＮ８の表面
の酸素もＡＬのぬれ性を向上させるから、ＡＬは容易に
コンタクト領域に侵入し、アスペクト比が１のサブミク
ロンホールも、空洞なく埋め込むことが可能になる。従
って最上層のＴｉＮ９も均一に表面に形成でき、ＡＬの
ヒロックが回避可能になる。一方、ＴｉＮ８は、グレイ
ンバウンダリに、Ｓ１原子とＯ原子とが存在するため、
ＡＬはＡｌ２Ｏ２またはＡＬ−５ｉをグレインバウンダ
リー中に形成し、グレインバウンダリー中に安定なＡＬ
２０３、ＡＬ−５ｉを形成した後は、ＡＬが侵入でき
ずそれ自身がＡＬ７の３１基板１へのスパイキングを回
避するバリアになる。また絶縁膜上のＴｉ４は、該ラン
プアニール時に、５ｉｎ２と反応しＴｉ酸化物１１を形
成するため配線と５ｉＯ２３の密着性を上げる。After this, 600
By performing short-time lamp annealing at a temperature of 1100 DEG C., the contact region changes to T1 silicide 6 and TiN 8, as shown in FIG. Furthermore, Si is diffused into the grain boundaries of the TiN in the contact region, resulting in TiN8 containing Si. Also SiO□
The Ti layer 4 on 3 reacts with O of SiO□ to form the Ti0 layer 11.
The upper layer reacts with N2 and changes to T i N4'. Further, due to the extremely low concentration 02 (≦10 ppm), the surface of TiN5' is slightly invaded by O atoms. After this, 250
A by heating sputtering or bias sputtering at temperatures above ℃
Accumulate alloys such as L or AL-Cu. At this time, Si atoms contained in TiN8 in the contact region are easily A
It penetrates into L, lowers the melting point of AL, and at the same time improves the wettability of AL. Furthermore, since the oxygen on the surface of TiN5' and TiN8 also improves the wettability of AL, AL easily invades the contact region, making it possible to fill even submicron holes with an aspect ratio of 1 without creating a cavity. Therefore, the top layer of TiN9 can also be formed uniformly on the surface, making it possible to avoid AL hillocks. On the other hand, TiN8 has S1 atoms and O atoms in the grain boundary, so
AL forms Al2O2 or AL-5i in the grain boundary, and stable AL forms in the grain boundary.
After forming 203 and AL-5i, AL cannot penetrate and itself becomes a barrier to avoid spiking of AL7 to 31 substrate 1. Furthermore, Ti4 on the insulating film reacts with 5in2 during lamp annealing to form Ti oxide 11, thereby increasing the adhesion between the wiring and 5iO23.
［発明の効果１
以上説明したように、本発明によれば、耐ＡＬスパイキ
ング、耐ヒロック、配線と眉間絶縁膜の密着性、そして
配線のステップカバレージ、すべてに優れた配線を持つ
高信斬性な半導体装置が可能になる。[Effects of the Invention 1] As explained above, the present invention provides a highly reliable wire that has excellent resistance to AL spiking, resistance to hillocks, adhesion between the wiring and the glabella insulating film, and step coverage of the wiring. This makes it possible to create highly flexible semiconductor devices.
第１．２図は本発明による半導体の断面図及び工程断面
図。
・３１基板
・拡散層
・層間絶縁膜
・Ｔｉ
・ＴｉＮ
・Ｔｉシリサイド
・ＡＬ金合
金ＳｉとＯ原子を含んだＴｉＮ
・コンタクト穴
・Ｏ原子を含んだＴｉＮ
・Ｔｉ０
ｋゲ
昂FIG. 1.2 is a sectional view and a process sectional view of a semiconductor according to the present invention.・31 substrate ・Diffusion layer ・Interlayer insulating film ・Ti ・TiN ・Ti silicide ・AL gold alloy TiN containing Si and O atoms ・Contact hole ・TiN containing O atoms ・Ti0 k gelation
Claims (3)
コン、シリサイド配線と接続するＡＬ配線領域は、高融
点金属シリサイドと高融点金属の窒化物とＡＬまたはＡ
Ｌ合金及び高融点金属の窒化物からなり、層間絶縁膜上
の配線領域は高融点金属の酸化物と高融点金属の窒化物
とＡＬまたはＡＬ合金及び高融点金属の窒化物から成る
ことを特徴とする半導体装置。(1) In IC wiring, the AL wiring region connected to the Si substrate, polycrystalline silicon, or silicide wiring is made of high melting point metal silicide, high melting point metal nitride, and AL or A
It is characterized by being made of an L alloy and a nitride of a high melting point metal, and the wiring region on the interlayer insulating film is made of a high melting point metal oxide, a high melting point metal nitride, and AL or an AL alloy and a high melting point metal nitride. semiconductor device.
続する領域の下層の高融点金属の窒化物には、Ｓｉ原子
が含まれることを特徴とする請求項１記載の半導体装置
。(2) The semiconductor device according to claim 1, wherein the refractory metal nitride in the lower layer of the region connected to the Si substrate, polycrystalline silicon, or silicide contains Si atoms.
窒化物にはＯ原子が含まれることを特徴とする半導体装
置。(3) A semiconductor device characterized in that the nitride of the lower layer high melting point metal contains O atoms in the entire wiring area of the IC.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63196495A JP2764934B2 (en) | 1988-08-06 | 1988-08-06 | Semiconductor device |
| US07/387,834 US4998157A (en) | 1988-08-06 | 1989-08-01 | Ohmic contact to silicon substrate |
| EP89307849A EP0354717A3 (en) | 1988-08-06 | 1989-08-02 | Semi-conductor device and method of manufacturing such a device |
| KR1019890011087A KR950013737B1 (en) | 1988-08-06 | 1989-08-03 | Semiconductor device having silicon-containing substrate and insulating film |
| US07/863,462 US5312772A (en) | 1988-08-06 | 1992-04-01 | Method of manufacturing interconnect metallization comprising metal nitride and silicide |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63196495A JP2764934B2 (en) | 1988-08-06 | 1988-08-06 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0245960A true JPH0245960A (en) | 1990-02-15 |
| JP2764934B2 JP2764934B2 (en) | 1998-06-11 |
Family
ID=16358721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63196495A Expired - Lifetime JP2764934B2 (en) | 1988-08-06 | 1988-08-06 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2764934B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04296020A (en) * | 1991-03-25 | 1992-10-20 | Nec Corp | Semiconductor device and manufactuer thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61183942A (en) * | 1985-02-08 | 1986-08-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS61290740A (en) * | 1985-06-19 | 1986-12-20 | Matsushita Electronics Corp | Manufacture of semiconductor device |
-
1988
- 1988-08-06 JP JP63196495A patent/JP2764934B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61183942A (en) * | 1985-02-08 | 1986-08-16 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS61290740A (en) * | 1985-06-19 | 1986-12-20 | Matsushita Electronics Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04296020A (en) * | 1991-03-25 | 1992-10-20 | Nec Corp | Semiconductor device and manufactuer thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2764934B2 (en) | 1998-06-11 |
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