JPH0247725A - data processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a data processing device that simultaneously decodes and processes two instructions.

2. Description of the Related Art In order to speed up processing in conventional data processing devices, a method has been adopted in which two decoders are provided to simultaneously decode two instructions and to operate two arithmetic units simultaneously. For example, in Japanese Patent Application Laid-Open No. 63-49843, two instructions, an arithmetic operation and a logical operation, are decoded by a first decoder and a second decoder, which are independent, respectively, and an arithmetic operation unit and a logical operation unit are decoded. Performance is improved by operating simultaneously.

In another example, a fixed size of instructions decoded multiple times is held in the decoded instruction buffer, and only when the instructions in the decoded instruction buffer can be used repeatedly by a loop, multiple decoded instructions are stored in the decoded instruction buffer. One method is to give a decoding instruction to the execution unit. (”TR0M
Based on specifications <32-bit microprocessor TX3 C
“Study of PU Architecture” IEICE Technical Research Report on Computer Systems, Yol, 8. No. 42
2.1988) Problems to be Solved by the Invention In conventional data processing devices, simultaneous decoding of two instructions in a fixed word length instruction system is easy because the position of the instruction following the instruction being decoded is fixed. It is. Therefore, simultaneous decoding of two instructions is possible by simply adding one second instruction decoder for decoding subsequent instructions. However, in order to suppress the increase in decoding hardware, the division of instructions to be decoded by each decoder is decided in advance, such as arithmetic operations and logical operations, so that the decoding hardware does not overlap in each decoder. There is. If the instructions to be decoded are divided between two decoders in this way, the increase in the hardware of the decoder can be suppressed, but it becomes difficult to always decode two instructions at the same time, and in some cases it becomes difficult to decode two instructions at the same time. It becomes necessary to decode twice. Therefore, it is necessary to take measures such as interleaving the two types of instructions based on the code schedule, which poses a problem of increasing the burden on the compiler.

In a variable word length instruction system, the position of the instruction following the instruction being decoded is determined by the decoding result of the instruction currently being decoded, so in order to decode two instructions simultaneously, the position of the instruction following the instruction being decoded is A plurality of second decoders that simultaneously decode the commands are provided, or a selector is provided to select the command word input to the second command decoder, and the selector is controlled according to the decoding result of the first command decoder. It was doing things like determining the input to the instruction decoder 2. Therefore, there are problems in that the hardware of the decoder increases and the time required for decoding increases. In addition, in the variable word length instruction system, 2
Since it is difficult to decode instructions simultaneously, the decoding results of each instruction are stored, and when the decoding results are supplied to the execution unit, two instructions are given at the same time to execute two instructions simultaneously. Ta. Therefore, a large capacity decoded instruction buffer was required. Furthermore, there is a problem in that the execution throughput is determined by decoding one instruction until the decoded instructions are accumulated in the decoded instruction buffer.

An object of the present invention is to provide a data processing device that can simultaneously decode two instructions in a variable word length instruction system without significantly increasing decoding hardware. Another object of the present invention is to provide a data processing device that simultaneously decodes a conditional branch instruction and the instruction following it and executes the conditional branch instruction at high speed.

Means for Solving the Problems In order to achieve the above object, the data processing device of the present invention includes a first instruction decoder for decoding instructions of a variable word length instruction system; a second instruction decoder that decodes an instruction that is subject to simultaneous decoding of two of the instructions;
a third instruction decoder that proactively detects the presence of an instruction that can be decoded by a second instruction decoder in a sequence of instructions following the instruction being decoded by the first instruction decoder; The detection result of the instruction decoder is validated by the output representing the instruction boundary of the first instruction decoder, and at the same time the third instruction decoder supplies the instruction being decoded to the second instruction decoder. and an instruction supplying means for controlling supply of subsequent instructions to the first instruction decoder.

Furthermore, in order to speed up conditional branch instructions, the data processing device of the present invention includes an adder that calculates the branch destination address of the conditional branch instruction, a comparator that detects whether the condition is satisfied, and a comparator that detects whether the condition is satisfied. branch control means for inhibiting execution of an instruction following the conditional branch instruction and at the same time starting processing of the instruction from the branch destination address of the adder only when the conditional branch instruction is executed.

Operation The present invention uses the above means to simultaneously decode two instructions in a variable word length instruction system without significantly increasing decoding hardware.

Furthermore, the execution speed of conditional branch instructions is improved, and when the condition is non-branch, the lock that is executed by the branch instruction with conditionality is apparently zeroed.

Embodiment FIG. 1 is a block diagram showing the configuration of a data processing apparatus according to an embodiment of the present invention. In the figure, 10 is an instruction fetch unit that fetches instructions in advance before execution; 11
is an instruction buffer that stores instructions prepared by the instruction fetch unit 10, and supplies instructions necessary for decoding to the decoder.

A first instruction decoder 12 decodes variable word length instructions, and decodes all instructions except the instruction that is subject to simultaneous decoding of two instructions. Reference numeral 13 denotes a second instruction decoder that decodes only the instruction that is subject to two-instruction simultaneous decoding; 14 and 16 decode the instruction word following the instruction being decoded by the first instruction decoder 12; This is a third instruction decoder that detects the presence of an instruction that is subject to simultaneous decoding of two instructions. 101 and 103 are the detection results. Reference numeral 17 denotes an instruction register that holds an instruction word to be decoded by the first instruction decoder 12 and an instruction word following it, and 18 is an instruction register that holds an instruction to be decoded by the second instruction decoder 13. Reference numeral 19 denotes an instruction supplying means control unit that shifts and controls the instruction registers 17 and 18, and outputs any one of the detection results 101 and 103 as valid through an output 100 without marking the instruction boundary decoded by the first instruction decoder 12. Then, the third instruction decoder that outputs a valid detection result controls to store the instruction being decoded into the instruction buffer 18. 20 is an instruction supply means for supplying instructions to the instruction decoders 12 and 16.

Reference numeral 21 denotes a decoded instruction register which temporarily holds the decoding results of the instructions decoded by the instruction decoders 12 and 13. 22 is an execution unit that executes an operation according to the contents of the command 104 of the decoded instruction register 21, and the A L necessary for execution.
U.

Including shifters, general purpose registers, etc. 23 is a branch destination address calculation means equipped with an adder 24 dedicated to address calculation, which executes a branch destination address 106 such as a conditional branch instruction or an unconditional branch instruction according to the contents of the command 105 of the decoding instruction register 21. 22 is calculated independently. 25
is a branch control means which inputs the condition code of the conditional branch instruction included in the command 107 of the decoded instruction register 21 and the operation result flag 108 output from the execution unit 22, and uses the comparator 26 to determine whether the branch condition is satisfied. Detect presence. When the branch condition is satisfied, a branch established signal 109 is used to suppress execution of the instruction following the branch instruction and at the same time control the instruction to be restarted from the branch destination address 106. Note that in the case of an unconditional branch instruction, the branch established signal 109 is always output. 27 is a bus transfer unit that controls data transfer with the outside of the processor. FIG. 2 is a diagram for explaining the operation when two variable word length instructions are simultaneously decoded by the data processing device of the present invention. The operation of the embodiment of the present invention will be explained below with reference to FIGS. 1 and 2.

FIG. 2 (1) is a diagram showing the order of instructions to be executed.
Execute instructions in order. Instruction sequence AO, A1, A2, A3
It is assumed that the AO instruction has a 16-bit displacement, and the A1 instruction is an instruction that is subject to simultaneous decoding of two instructions. Therefore, it is assumed that the A1 instruction and the A2 instruction are decoded at the same time. FIG. 2(2) is a diagram showing the states of the instruction registers 17 and 18 while the first instruction decoder is decoding the AO instruction. In the four 16-bit instruction registers IRQ and IR3 constituting the instruction register 17, an AO instruction is stored in IRQ, a displacement of the AO instruction is stored in IR1, an A1 instruction is stored in IR2, and an A2 instruction is stored in IR3 in the order of instruction strings. At this time, the first instruction decoder 12
It decodes Q's AO instruction and outputs a signal 100 indicating that the instruction boundary is between IRI and IR2. In parallel with this, the third instruction decoders 14 to 16 are respectively IRI to I
R3 displacement, AI instruction, A2 respectively
It decodes the instructions, checks whether there is an instruction that is subject to two-instruction simultaneous decoding, and outputs the result to signal lines 101 and 103. At this time, since the third instruction decoders 14 to 16 do not recognize the instruction boundaries, if the displacement value of the IRI coincidentally matches the code of the instruction that is the target of simultaneous decoding of two instructions, the third The instruction decoder 14 of No. 3 outputs an erroneous detection result to the signal line 101. The instruction supply means control unit 19 eliminates erroneous detection results from the signal lines 101 and 103 using the signal 100 indicating the boundary of the instruction, and determines that the detection result 102 is valid. Based on this, the instruction registers 17 and 18 are shifted and controlled, and the instruction A1 of IR2 is transferred to the instruction register 18, and the instruction A2 of the subsequent IR3 is transferred to the instruction register 18.
is stored in the instruction register IRQ. The state is shown in Figure 2 (
3). In the state shown in (3) of the same figure, the first instruction decoder 12
decodes the A2 instruction, and the second instruction decoder 13 decodes the A1 instruction, thereby simultaneously decoding two instructions. In addition,
The third instruction decoders 14 and 16 only detect the presence or absence of instructions that can be decoded simultaneously, and can be realized by hardware with several gates. In addition, the second instruction decoder decodes only the instruction that is the target of two-instruction simultaneous decoding, and the first instruction decoder only has to decode instructions other than the target instruction, so the amount of decoding hardware increases. do not.

Next, FIGS. 3 and 4 are diagrams for explaining the operation when the data processing device of the present invention speeds up conditional branch instructions. FIG. 3 is a diagram showing the order of a sequence of instructions to be executed, FIG. 4 (1) is an operation timing diagram when the condition is not met, and FIG. 4 (2) is an operation timing diagram when the condition is met.

The operation of the conditional branch instruction will be explained below with reference to FIGS. 1, 3, and 4.

FIG. 3 shows a sequence of instructions to be executed, indicating that when the condition of a conditional branch instruction (B c c ) is met, the program branches to the B1 instruction, and when the condition is not met, the subsequent A1 instruction is executed. The instruction decoder simultaneously decodes the conditional branch instruction and the following A1 instruction. In FIG. 4, IF indicates the operation of the instruction fetch unit 10, and D
EC indicates the operation of the instruction decoder. R, EX, and W indicate the operations of the execution unit 22, and represent register reading, operation, and register writing, respectively. The AO instruction decoded at timing 2 is operated on at timing 4, and the result is written at timing 5.

At the same time, the calculation result flag is output to the signal line 108.

On the other hand, at timing 3, the conditional branch instruction and the following A1 instruction are simultaneously decoded, and the decoded result is stored in the decoded instruction register 21. At timing 4, according to the contents of the decoded instruction register 21, the branch destination address calculation means 2
The address of the B1 instruction is calculated and temporarily held in the adder 24 dedicated to address calculation. Furthermore, in the execution unit 22, the contents of registers necessary for the operation of the AI instruction are read. At timing 5, execution unit 22
The operation of the A1 instruction is performed and the operation result is temporarily held. At the same time, the comparator 26 of the branch control means 25 compares the condition code of the conditional branch instruction with the AO calculated at timing 4.
It is compared with the operation result flag 108 of the instruction. If the comparison result does not satisfy the condition, the operation result of the A1 instruction held at timing 5 is written to the register at timing 6. Furthermore, B1 calculated at timing 4
The instruction address is invalidated and the instruction fetch unit 10
continues fetching the instruction sequence following the conditional branch instruction. If the comparison result condition is satisfied, writing of the operation result of the A1 instruction at timing 6 is prohibited, and execution of all subsequent instructions is invalidated. Then, the instruction fetch unit 10 fetches the 81st instruction according to the address of the B1 instruction calculated at timing 4, and processing is started.

With the above-described configuration, the present invention can handle two instructions without significantly increasing the decoding hardware in a variable word length instruction system.
It is an object of the present invention to provide a data processing device that simultaneously decodes instructions and executes conditional branch instructions at high speed. For this purpose, a first instruction decoder that decodes the instructions of the variable word length instruction system, and two of the instructions of the variable word length instruction system are provided.
a second instruction decoder that decodes an instruction that is subject to instruction simultaneous decoding; and a second instruction decoder that decodes an instruction that can be decoded by the second instruction decoder in an instruction sequence that follows the instruction that is being decoded by the first instruction decoder. a third instruction decoder that proactively detects the presence of the third instruction decoder;
The detection result of the instruction decoder is validated by the output representing the instruction boundary of the first instruction decoder, and at the same time the third instruction decoder supplies the instruction being decoded to the second instruction decoder. an instruction supply means for controlling supply of a subsequent instruction to a first instruction decoder; an adder for calculating a branch destination address of a conditional branch instruction; a comparator for detecting whether a condition is satisfied; and a branch control means that inhibits the execution of an instruction following a conditional branch instruction only when the conditional branch instruction is executed, and at the same time starts processing the instruction from the branch destination address of the adder, thereby significantly increasing the amount of decoding hardware. Since two instructions can be decoded simultaneously, processing speed can be increased. Furthermore, the execution speed of conditional branch instructions can be increased, and especially when the condition is not met, the execution time can be reduced to an apparent zero.

Effects of the Invention As described above, according to the present invention, by providing a third instruction decoder to proactively detect the existence of an instruction that can decode two instructions simultaneously, variable decoding hardware can be suppressed and It is possible to simultaneously decode two word-length instructions, resulting in faster processing.

Furthermore, the processing of conditional branch instructions can be sped up by simultaneously decoding two instructions of a conditional branch instruction and the instruction that follows it, and by inhibiting the execution of all subsequent instructions when the condition is met. Note that by providing two arithmetic execution units and simultaneously decoding the inter-register arithmetic instruction and the instruction following it, it is also possible to execute the two instructions in parallel when register resources do not interfere.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a data processing device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram of operation when two variable word length instructions are simultaneously decoded by the data processing device of the present invention, and FIG. 3 is a condition diagram. FIG. 4 is an instruction diagram showing an execution instruction sequence to explain the operation when a conditional branch instruction is sped up by the data processing device of the present invention. FIG. It is a diagram. 10... Instruction fetch unit, 11... Instruction buffer 12... First instruction decoder, 13... Second instruction decoder, 14.15.16... Third instruction decoder , 20...
Instruction supply means, 21... Decoded instruction register, 22... Execution unit, 23... Branch destination address calculation means, 24... Adder, 25... Branch control means, 26...
・Comparator. Name of agent: Patent attorney Shigetaka Awano 1 person Figure 1 Figure a) Now 2\夛（Hitting power is 1）子Ao Soukyou/l屏跣Aノ 4/Ri＼3 A24＼I〉5 ．． Luna Saitei Voice Expo ξ Floating Diagram

Claims (2)

[Claims] (1) a first instruction decoder that decodes an instruction of a variable word length instruction system; a second instruction decoder that decodes an instruction that is subject to simultaneous decoding of two instructions among the instructions of the variable word length instruction system; 1st
a third instruction decoder that proactively detects the presence of an instruction that can be decoded by a second instruction decoder in a sequence of instructions that follows an instruction that is being decoded by the instruction decoder; The third instruction decoder supplies the instruction being decoded to the second instruction decoder, and at the same time the third instruction decoder supplies the instruction being decoded to the second instruction decoder, and at the same time outputs the instruction subsequent to the instruction. and an instruction supply means for controlling the supply of the instruction to the first instruction decoder, and the data processing device is characterized in that the first instruction decoder and the second instruction decoder decode two instructions at the same time. . (2) an adder that calculates the branch destination address of a conditional branch instruction; a comparator that detects whether the condition is satisfied; 2. The data processing apparatus according to claim 1, further comprising branch control means for starting instruction processing from a branch destination address of said adder, and for simultaneously executing a conditional branch instruction and its successor instruction.