JPH0247974A - Image signal binarization circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an image signal binarization circuit, and more specifically, it compares an analog image signal with a predetermined comparison reference value to perform black and white binarization processing. The present invention relates to an image signal binarization circuit.

(Prior Art) In the scanner section of a facsimile machine, scanner device, etc., C, CD (Charge Coupled D
An image signal binarization circuit is provided that converts an analog image signal read by a photoelectric conversion means such as an electronic device (device) into a black and white binary signal.

That is, a photoelectric conversion means such as COD divides reflected light from a light source onto a document into a plurality of pixels, performs photoelectric conversion for each pixel, and outputs it as an analog image signal. The analog image signal read in this manner is binarized by an image signal binarization circuit and then subjected to subsequent processing such as transmission.

In such an image signal binarization circuit, an analog image signal is compared with a predetermined comparison reference value and binarized.
In this case, in order to reduce the influence of non-uniformity of the light source, non-uniformity of the sensitivity of the photoelectric conversion means, etc., conventionally the peak value of the analog image signal is detected, and the reference value for comparison is determined based on this peak value. Settings are being done.

(Problem to be Solved by the Invention) However, in such conventional image signal binarization circuits, the comparison reference value was set only based on the peak value of the analog image signal, so fine details such as thin lines etc. There was a problem in that it was not possible to accurately read changes in the image, resulting in poor image quality.

In other words, images read by a scanner section of a facsimile machine or a scanner device generally have degraded spatial frequency characteristics, and the MTF (Modulation Tran)
sfer Function: Fourier transform of the fish bed density function and its absolute value) is low. This MT
When F is low, it is easy to be influenced by surrounding pixels, and it is not possible to accurately binarize thin white or black lines. Also,
When reading an image by moving a photoelectric conversion means in which one line of photoelectric conversion elements is arranged in the main scanning direction in the sub-scanning direction, the MT in the sub-scanning direction is smaller than the MTF in the main scanning direction.
F is lower, and thin horizontal lines cannot be binarized accurately. As a result, there was a problem in that detailed images could not be read accurately and the image quality was poor.

(Object of the Invention) Therefore, the present invention provides a method of setting a comparison reference value for comparing an image signal based on the value of the binarized output of the previous pixel of the image signal or the pixel at the same position in the previous line. , the purpose is to improve image quality by reading fine images such as thin lines with high accuracy even when the MTF is low.

(Structure of the Invention) In order to achieve the above object, the present invention provides: (1) an image signal binarization circuit that compares an input analog image signal with a predetermined comparison reference value and performs binarization processing;
Two types of comparison reference values are set, a first comparison reference value closer to the white side and a second comparison reference value closer to the black side, and these first comparison reference values and the second comparison reference value are set. Based on which comparison reference value of the value (binarized output is output,
The method is characterized in that the determination is made based on the value of the binarized output of the pixel before the pixel currently being processed.

and (2) an image signal binarization circuit that compares the input analog image signal with a predetermined comparison reference value and performs binarization processing,
Two types of comparison reference values are set, a first comparison reference value closer to the white side and a second comparison reference value closer to the black side, and these first comparison reference values and the second comparison reference value are set. Select which comparison reference value to output the binarized output based on.
This is characterized in that the determination is made based on the value of the binarized output of the pixel at the same position in the line preceding the pixel currently being processed.

Hereinafter, a detailed description will be given based on examples.

FIG. 1 is a diagram showing an embodiment of the invention according to claim 1.

In FIG. 1, the image signal binarization circuit 1 includes a comparator 2.3.
, a first reference value generator 4, a second reference value generator 5, a selection circuit 6, a shift register 7, and the like.

Analog image signals GS read by a photoelectric conversion means such as a CCD (not shown) are input serially to the comparators 2 and 3 for each pixel, and the comparators 2 and 3 are also input with the first
A first comparison reference value SL from the reference value generator 4 is supplied to the comparator 3, and a second comparison reference value SL from the second reference value generator 5 is supplied to the comparator 3.
is entered.

The first reference value generator 4 generates a first comparison reference value SL, which becomes a reference for binarization in the comparator 2, and the first comparison reference value SL,
As shown in FIG. 2, SL is set to a value closer to the black level than the second comparison reference value SL. A second reference value generator 5 has a second comparison reference value S that serves as a reference for binarization in the comparator 3.
As shown in FIG. 2, the second comparison reference value SL is set to a value closer to the white level than the first comparison reference value SL. The comparator 2 compares the image signal GS with a first comparison reference value SL, performs black and white binarization processing, and outputs the binarized image signal to the selection circuit 6. Comparator 3 receives image signal GS
is compared with a second comparison reference value S L z, black and white binarization processing is performed, and a binarized image signal is output to the selection circuit 6. A selection circuit 6 selects either the binary image signal from the comparator 2 or the binary image signal from the comparator 3 to produce a binary output image signal B.
Output as S. The binarized output image signal BS from the selection circuit 6 is also input to a shift register 7, and the shift register 7 receives the binarized output image signal B input from the selection circuit 6.
S is latched and output to the selection circuit 6.

The selection circuit 6 selects the binary image signal from the comparator 2 and the binary image from the comparator 3 which are input at the next pixel timing based on the binary output image signal BS from the shift register 7. It is determined which of the signals will be adopted as the binarized output image signal BS.

Next, the action will be explained.

At a predetermined pixel timing, the analog image signal GS is input to the comparator 2, and the first comparison reference value S
L, is input from the first reference value generator 4, and the comparator 2 binarizes the image signal GS based on the first comparison reference value SL, and outputs the binarized image signal to the selection circuit 6. . On the other hand, at the same pixel timing, the comparator 3 receives the same image signal GS.
At the same time, the second comparison reference value SL2 is input from the second reference value generator 5, and the comparator 3 performs binarization processing on the image signal GS based on the second comparison reference value SL. The converted image signal is output to the selection circuit 6.

The selection circuit 6 receives the binary output image signal BS outputted by the selection circuit 6 at the previous pixel timing from the shift register 7, and the selection circuit 6 inputs the binary output image signal BS from the shift register 7. Based on this, one of the binary image signal from the comparator 2 and the binary image signal from the comparator 3 is selected and output as the binary output image signal BS. That is, the selection circuit 6 determines which of the first comparison reference value SL and the second comparison reference value SL to output the binarized output based on, based on which of the binarized output of the previous pixel currently being processed. (Binarized output image signal B
As shown in FIG. 3, when the previous pixel (binarized output image signal BS) is black, the binary image signal is determined based on the first comparison reference value SL. When the previous pixel (binarized output image signal BS) is white, the binary image signal based on the second comparison reference value SL2 is adopted. Therefore, even a fine image such as a thin line can be read with high precision by separating it from the previous pixel, and the image quality can be improved.

FIG. 4 is a diagram showing another embodiment of the image signal binarization circuit of the invention as claimed in claim 1.
Components that are the same as those of the embodiment shown in FIGS. 3 to 3 are designated by the same reference numerals, and their explanations will be omitted.

In FIG. 4, the image signal binarization circuit 11 includes a comparator 12,
First reference value generator 4, second reference value generator 5, selection circuit 1
3 and a shift register 7.

The selection circuit 13 is manually supplied with the first comparison reference value SL from the first reference value generator 4 and the second comparison reference value SL2 from the second reference value generator 5. One of the first comparison reference value SL from the reference value generator 4 and the second comparison reference value SL from the second reference value generator 5 is based on the binarized output image signal BS from the shift register 7. selects one and outputs it to the comparator 12. The image signal GS and the comparison reference value from the selection circuit 13 are input to the comparator 12, and the comparator 12 compares the image signal GS with the comparison reference value from the selection circuit 13 to perform binarization processing. Comparator 12 is 2
The binarized output image signal BS that is digitized and output is also input to the shift register 7, latched by the shift register 7, and output to the selection circuit 13.

Therefore, in this embodiment, the comparator 12 binarizes both signals GS based on the comparison reference value from the selection circuit 13 and outputs the binarized output image signal BS. The selection circuit 13 selects the binary output image signal BS from the shift register 7, that is, 2 of the previous pixel currently being processed.
The first comparison reference value SL and the second comparison reference value SL are selected based on the digitized output.

As shown in FIG. 2, these first comparison reference value SL and second comparison reference value S L z are set to a value closer to the black level as the first comparison reference value SL, and a value closer to the black level is set as the first comparison reference value SL. The comparison reference value SL is set to a value closer to the white level than the border.

Similarly to the process of the flowchart shown in FIG. If the previous pixel is white, the second comparison reference value SL2 from the second reference value generator 5 is adopted and output to the comparator 12. That is, also in the zero picture signal binarization circuit 11,
Based on the binarized output of the pixel before the pixel currently being processed, it is determined which of the first comparison standard value SL and the second comparison standard value SL2 to output the binarized output based on. ing. As a result, it is possible to read fine images such as thin lines with high precision by separating them from the previous pixel, and the image quality can be improved.

Furthermore, in this embodiment, the binarization process can be performed with only one comparator, and the circuit configuration can be simplified. As a result, the image signal binarization circuit 11 can be made inexpensive.

FIG. 5 is a diagram showing an embodiment of the invention as claimed in claim 2, and the same components as those in the embodiment shown in FIGS. 1 to 3 are given only the same reference numerals, and their explanations are omitted. .

In FIG. 5, the image signal binarization circuit 21 includes comparators 2.
3, a first reference value generator 4, a second reference value generator 5, a selection circuit 22, a line buffer memory 23, and the like.

The selection circuit 22 receives the binarized image signals from the comparators 2 and 3 manually, and the line buffer memory 23
The selection circuit 22 inputs the binary output image signal BS from the line buffer memory 23 manually.
Based on this, one of the binary image signal from comparator 2 and the binary image signal from comparator 3 is selected and the binary output image signal BS is generated.
Output as .

The binarized output image signal BS outputted from the selection circuit 22 is also input to the line buffer memory 23, and the line buffer memory 23 has a capacity to store the binarized output image signal BS for one line. Therefore, the line buffer memory 23 outputs the binarized output image signal BS at the same position one line before the image signal currently being processed by the selection circuit 22 to the selection circuit 22, and the selection circuit 22 outputs the first comparison reference value SL. , and the second comparison reference value S L z to output the binary output based on the binary output of the pixel at the same position one line before the pixel currently being processed (binary output). converted output image signal BS)
Determine based on the value of .

The selection circuit 22 makes this decision, as shown in the flowchart of FIG. If the value of the previous line is white, the binary image signal from the comparator 3 based on the second comparison reference value SL is output as the binary output image signal BS.

Therefore, it is possible to accurately read fine images such as thin lines by separating them from the pixels of the previous line, and the image quality can be improved.

FIG. 7 is a diagram showing another embodiment of the invention as claimed in claim 2. In explaining this embodiment, the same components as in each embodiment shown in FIG. 5.6 are given the same reference numerals. Therefore, the explanation will be omitted.

In FIG. 7, the image signal binarization circuit 41 includes a comparator 32
, a first reference value generator 4, a second reference value generator 5, a selection circuit 33, a line buffer memory 23, and the like.

The selection circuit 33 selects a first comparison reference value SL from the first reference value generator 4 and a second comparison reference value from the second reference value generator 5 based on the binarized output image signal BS from the line buffer memory 23. One of the values SL2 is selected and output to the comparator 32, and the image signal GS is further input to the comparator 32. The comparator 32 compares the image signal GS with a comparison reference value from the selection circuit 33, performs binarization processing, and outputs the result as a binarized output image signal BS. This binarized output image signal BS is also input to the line buffer memory 23, delayed by one line in the line buffer memory 23, and input to the selection circuit 33.

Therefore, the image signal binarization circuit 31 uses the first comparison reference value S
1 of the pixels currently being processed to determine which comparison reference value to output the binarized output based on, L, and the second comparison reference value SL.
Binarized output of the pixel before the line (binarized output image signal BS)
As shown in FIG. 6, if the previous line is black, the selection circuit 33
outputs the first comparison reference value SL to the comparator 32 and outputs a binarized output image signal BS based on the first comparison reference value SL+,
If the previous line is white, the selection circuit 33 outputs the second comparison reference value SL2 to the comparator 32, and outputs a binarized output image signal BS based on the second comparison reference value SL2.

Therefore, it is possible to accurately read fine images such as thin lines and improve the image quality, and it is also possible to perform binarization processing with only one comparator 32, making the image signal binarization circuit 31 inexpensive. It can be done.

8 to 10 are diagrams showing an embodiment of the invention in which the invention according to claim 1 and the invention according to claim 2 are combined.

In FIG. 8, the image signal binarization circuit 41 includes a comparator 42
．． 43.44.45, first reference value generator 46, second reference value generator 47, third reference value generator 48, fourth reference value generator 49, selection circuit 50, shift register 51 and line buffer 5' It is equipped with 2nd class.

The image signal GS is input to each comparator 42, 43, 44, 45, and the first reference value generator 46 is input to the comparator 42.
The comparator 43 receives the first comparison reference value SL from the second reference value generator 47 .

However, the third comparison reference value SLe from the third reference value generator 48 is input to the comparator 44, and the fourth comparison reference value SL from the fourth reference value generator 49 is input to the comparator 45. There is. As shown in FIG. 9, the reference value generators from the first reference value generator 46 to the fourth reference value generator 49 sequentially approach the white level from the first comparison reference value SL, which is closer to the black level. Second comparison standard value SL, third comparison standard value SLC
and a fourth comparison reference value SL. Comparator 42~
The comparators 45 respectively compare the first comparison reference value SL to the fourth comparison reference value SL with the image signal GS, perform binarization processing, and output the binarized image signal to the selection circuit 50 . The selection circuit 50 includes a shift register 51 and a line buffer 5.
The selection circuit 50 receives the binary output image signal BS from the shift register 51 and the line buffer 52 based on the binary output image signal BS from the comparators 42 to 45. A digitized image signal is selected and outputted as a binarized output image signal BS. This binary output image signal BS is also input to the shift register 51 and line buffer 52, the shift register 51 latches this binary output image signal BS and outputs it to the selection circuit 50, and the line buffer 52 It is output to the selection circuit 50 with a delay of 10 minutes.

Therefore, the selection circuit 50 selects the binary image signals inputted from the comparators 42 to 45 based on the binary output image signals BS of the pixel before the pixel currently being processed and the pixel one line before. Then, it is output as a binarized output image signal BS.

Then, as shown in FIG. 10, when the previous line pixel and the previous pixel are both black, the selection circuit 50 adopts the binarized image signal based on the first comparison reference value SL as the binarized output image signal BS. However, when the previous line pixel is black and the previous pixel is white,
The binarized image signal based on the second comparison reference value SLb is employed as the binarized output image signal BS. Furthermore, when the previous line pixel is white and the previous pixel is black, the binarized image signal based on the third comparison reference value SL0 is adopted as the binarized output image signal BS, and both the previous line pixel and the previous pixel are white. At this time, the binarized image signal based on the fourth comparison reference value SL is adopted as the binarized output image signal BS. As a result, even fine images such as thin lines can be read accurately by separating the previous pixel and the previous line pixel, and the image quality can be further improved.

FIG. 11 is a diagram showing another embodiment of the invention that combines the invention claimed in claim 1 and the invention claimed in claim 2. In explaining this embodiment, the embodiment shown in FIGS. Components that are the same as those in the example are given the same reference numerals and their explanations will be omitted.

In FIG. 11, the image signal binarization circuit 61 includes a comparator 6
2. Equipped with a first reference value generator 46, a second reference value generator 47, a third reference value generator 48, a fourth reference value generator 49, a selection circuit 63, a shift register 51, a line buffer 52, etc. .

The selection circuit 63 receives a first comparison reference value SL, a second comparison reference value from a first reference value generator 46, a second reference value generator 47, a third reference value generator 48, and a fourth reference value generator 49. SL
,, a third comparison standard value SLc and a fourth comparison standard value SL,
is input, and a binarized output image signal BS is also input from the shift register 51 and line buffer 52. ,
One of the first comparison reference values SL to the fourth comparison reference values SL is selected and output to the comparator 62. Comparator 62
Further, the image signal GS is inputted to the comparator 6.
2 binarizes the image signal GS based on the comparison reference value inputted from the selection circuit 63 and outputs a binarized output image signal BS. The binarized output image signal BS from the comparator 62 is also input to the shift register 51 and the line buffer 52, from the shift register 51 as the binarized output image signal BS of the previous pixel, and from the line buffer 52 to the previous line. is outputted to the selection circuit 63 as a binarized output image signal BS of the pixel. The selection circuit 63 selects the previous pixel and the previous line pixel.
Based on the digitized output image signal BS, the first reference value generator 46~
The first comparison reference value S input from the fourth reference value generator 49
L, - second comparison reference value SL is selected and output to the comparator 62, and this selection is determined in the same manner as in the flowchart shown in FIG.

Therefore, in this embodiment as well, it is possible to select the binarized output image signal BS based on the comparison reference value based on the binarized output image signal BS of the previous pixel and the previous line pixel, and one line buffer 52 can select the binarized output image signal BS. The image signal binarization circuit 51
can be made inexpensive.

(Effects) According to the present invention, even when M TF is low, even fine images such as thin lines can be read with high accuracy, and image quality can be improved.

[Brief explanation of the drawing]

1 to 3 are diagrams showing an embodiment of the image signal binarization circuit of the invention as claimed in claim 1, FIG. 1 is a block diagram of the circuit, and FIG. 2 is a first comparison reference value thereof. FIG. 3 is a flow chart showing the selection process based on the value of the previous pixel. FIG. 4 is a circuit block diagram of another embodiment of the image signal binarization circuit according to the first aspect of the invention. 5.6 is a diagram showing an embodiment of the image signal binarization circuit of the invention as claimed in claim 2, FIG. 5 is a block diagram of the circuit, and FIG. 6 is a selection process based on the previous line pixel. It is a flowchart which shows. FIG. 7 is a circuit block diagram of another embodiment of the image signal binarization circuit according to the second aspect of the invention. 8 to 10 are diagrams showing an embodiment of an image signal binarization circuit of the invention that combines the invention described in claim 1 and the invention described in claim 2, and FIG. 8 is a block diagram of the circuit. 9 is a diagram showing the relative relationship from the first comparison reference value to the fourth comparison reference value, and FIG. 10 is a flowchart showing the selection process based on the values of the previous pixel and the previous line pixel. FIG. 11 is a circuit block diagram of another embodiment of the image signal binarization circuit according to the invention, which is a combination of the invention as claimed in claim 1 and the invention as claimed in claim 2. 1.11.21.31.41.51... Image signal binarization circuit, 2.3.12.32.42.43.44.
45.62... Comparator, 4... First reference value generator, 5... Second reference value generator, 6.13.22.33.50. 63... Selection circuit, 7.51... Shift register, 23.52
・・・・・・Line Ha Sofa Memory, 46・・・・・・
1st reference value generator, 47...2nd reference value generator, 48...3rd reference value generator, 49...4th reference value generator.

Claims (2)

[Claims] (1) In an image signal binarization circuit that performs binarization processing by comparing an input analog image signal with a predetermined comparison reference value,
Two types of comparison reference values are set, a first comparison reference value closer to the white side and a second comparison reference value closer to the black side, and these first comparison reference values and the second comparison reference value are set. Select which comparison reference value to output the binarized output based on.
An image signal binarization circuit characterized in that the image signal binarization circuit determines the value based on the value of the binarization output of the pixel before the pixel currently being processed. (2) In an image signal binarization circuit that compares an input analog image signal with a predetermined comparison reference value and performs binarization processing,
Two types of comparison reference values are set, a first comparison reference value closer to the white side and a second comparison reference value closer to the black side, and these first comparison reference values and the second comparison reference value are set. Select which comparison reference value to output the binarized output based on.
An image signal binarization circuit characterized in that the image signal binarization circuit determines the value based on the value of the binarization output of a pixel at the same position in the line preceding the pixel currently being processed.