JPH0249012B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a semiconductor device that performs high-concentration ion implantation using a shottock junction electrode as a mask to reduce series resistance without deteriorating the reverse withstand voltage of the shottock junction. Specifically,
The present invention relates to a method for manufacturing a Schottky junction diode and a Schottky junction gate field effect transistor using a compound semiconductor.

Integrated circuit (abbreviated as IC) using semi-insulating (abbreviated as S, I) gallium arsenide (abbreviated as GaAs)
development is underway. The ways to reduce the series resistance of the field effect transistor (abbreviated as FET) and Schottky diode (abbreviated as SB Di), which are the constituent elements of this IC, are: (1) shorten the distance between the ohmic electrode and the Schottky junction electrode; (2) Increase the carrier concentration in the region where the ohmic electrode is to be formed and reduce the ohmic contact resistance. (3) Increase the carrier concentration in the GaAs active layer between the ohmic electrode and the Schottky junction electrode or (4) Increasing the thickness of the GaAs active layer in which the ohmic electrode is to be formed may be considered. Currently, method (4) is generally adopted. FIG. 1 shows a cross-sectional view of an FET using method (4) above. As shown in Figure 1, S, I, GaAs
1 and a channel below the shot junction gate electrode 2. Below the GaAs active layer region 3 and the source electrode 4 and drain electrode 5, which are ohmic electrodes, are connected to the GaAs active layer region 3.
Another layer thicker than the thickness of the GaAs active layer region
A GaAs active layer region 6 is formed. The formation of such a GaAs active layer is generally performed by adding silicon (Si) or selenium (Se), which becomes N-type ions, to S, I, or GaAs.
This is done by annotating ions. Said
It is clear from (3) of the series resistance reduction measure above that the series resistance can be reduced by making the length of the GaAs active layer 3 approximately the same as the gate length, but the alignment with the gate electrode 2 However, it is difficult to make the GaAs active layer 3 longer than the gate by 2 μm or more.

The purpose of the present invention is (2) of the above-mentioned series resistance reduction measures.
It is an object of the present invention to provide a method for manufacturing a semiconductor device that satisfies both (3) and (4) and further reduces the series resistance formed by conventional methods.

According to the present invention, a step of forming a shot junction electrode on an active layer of a semiconductor, a step of depositing a metal or an insulating material on the active layer of the semiconductor to cover the electrode, and a step of depositing a metal or an insulating material on the active layer of the semiconductor; A step of removing the metal or insulator remaining only in the vicinity of the electrode using a dry etching method, and using the electrode as a mask to form an N-type or P-type impurity. a step of implanting ions into the semiconductor; a step of removing the metal or the insulator remaining only in the vicinity of the electrode and then annealing to activate the ion-implanted semiconductor region; A method for manufacturing a semiconductor device is obtained, which comprises a step of providing an ohmic electrode in a semiconductor region.

This will be explained below using the drawings.

Figure 2 is a diagram for explaining the present invention.
An example applied to manufacturing an FET will be described.
First, as shown in FIG ^.
-3 , a shot junction electrode 3 is formed on the N-type GaAs active layer 2 with a thickness of 0.15 μm using, for example, an alloy of titanium and tungsten (abbreviated as Tiw). The material of the shottock junction electrode has high heat resistance against GaAs, and even after annealing at 900°C for several tens of minutes, the electrical properties of the shottock junction do not deteriorate significantly compared to the characteristics before annealing, resulting in a good shottock junction. It is necessary to show the Generally, the gate length of FET used for GaAsIc is 0.5 to 1.0μ. Next, as shown in FIG. 2b, a metal 4, such as aluminum (abbreviated as Al), is placed on the N-type GaAs active layer 2, covering the shot junction electrode 3.
is deposited using, for example, a vacuum evaporation method using a evaporation apparatus equipped with a planetarium or a sputtering method. At this time, it is important that the metal deposited on the side surface 5 of the shot junction electrode 3 is not significantly thinner than the thickness of the metal deposited on other parts. Next, as shown in FIG. 2c, the metal 4
is removed using an anisotropic dry etching technique.
If the connection is made from the direction perpendicular to
The thickness of the metal 4 deposited on the side surface 5 of the S, I, GaAs substrate 1 in the direction perpendicular to the shot junction electrode 3 is
Since the metal 4 is thicker than the metal 4 on the N-type GaAs active layer 2 except for the upper surface 6 and the vicinity of the shot junction electrode 3, a portion 7 of the metal 4 attached to the side surface 5 of the shot junction electrode 3 remains. Next, as shown in FIG. 2d, using the shot junction electrode 3 and a part 7 of the metal 4 as a mask,
I, for example, Si, which becomes N-type ions on the GaAs substrate 1
For example, acceleration energy 120KeV dose 5×
10 ¹³ cm ^-2 , then ion implantation is performed under the conditions of acceleration energy of 50 keV and dose of 1×10 ¹³ cm ^-2 to form the ion implanted layer 8. When the ion-implanted layer 8 implanted under the above conditions was annealed to activate the ion-implanted layer 8 and become an N-type GaAs operating layer, the activation rate was about 65%. Next, as shown in FIG. 2e, a portion 7 of the metal 4 is etched away using, for example, phosphoric acid, and then, for example, in an arsenic atmosphere.
By annealing at 850° C. for 15 minutes, the ion-implanted layer 8 is converted into an N-type GaAs operating layer 9.
Under such annealing conditions, an activation rate of about 65% or more can be obtained. Next, as shown in Figure 2 f,
For example, a gold-germanium alloy is deposited and alloyed on the N-type GaAs active layer 9, and an ohmic electrode 10 is formed to form an FET. In order to reduce the series resistance, it is necessary to increase the carrier concentration of the N-type GaAs operating layer 9 and make it thick (corresponding to the series resistance reduction measures (3) and (4) above), and the surface concentration It is important to increase the resistance (corresponding to the series resistance reduction measure (2) mentioned above). These requirements are determined by the ion implantation conditions, that is, the acceleration energy and dose during ion implantation, the number of times of implantation, the degree of overlap of ion implanted layers, etc. On the other hand, the closer the length of the N-type GaAs active layer 2 is to the length of the shot junction electrode 3, the lower the series resistance is.
The distance between the shot junction electrode 3 and the shot junction electrode 3 depends on the thickness of the shot junction electrode 3 and the thickness of the metal 4.

In FIG. 2, when an insulating film such as silicon dioxide or silicon nitride was used in place of the metal 4, the same results as with metal were obtained.

This manufacturing method is not only suitable for manufacturing GaAs FETs, but also
It is clear that this method is also suitable for manufacturing FETs and diodes made using semiconductors such as InP.

In this manufacturing method, it is not necessary to position the shot junction electrode and the ohmic electrode very close to each other in order to reduce the series resistance, and since the alignment of these electrodes is simple, the alignment can be automated. , uniformity of performance can be achieved, and a high manufacturing yield can be obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a field effect transistor manufactured by a conventional manufacturing method, and FIG. 2 is a diagram for explaining an embodiment of the present invention. In the figure, 1 is an S, I, GaAs substrate, 2 is an active layer, 3 is a shot junction electrode, 4 is a metal, and 8 is an ion-implanted layer.

Claims (1)

[Claims] 1. A step of forming a shot junction electrode on the active layer of a semiconductor, a step of depositing a metal or an insulating material on the active layer of the semiconductor to cover the electrode, and a step of etching the metal or the insulating material by an anisotropic dry etching method. A step of removing the metal or the insulator remaining only in the vicinity of the electrode and the electrode is used as a mask to remove ions that can become N-type or P-type impurities from the semiconductor. a step of activating the ion-implanted semiconductor region by annealing after removing the metal or the insulator remaining only in the vicinity of the electrode, and activating the ion-implanted semiconductor region; A method for manufacturing a semiconductor device, comprising the step of providing an ohmic electrode.