JPH0249230U - - Google Patents
Info
- Publication number
- JPH0249230U JPH0249230U JP12713888U JP12713888U JPH0249230U JP H0249230 U JPH0249230 U JP H0249230U JP 12713888 U JP12713888 U JP 12713888U JP 12713888 U JP12713888 U JP 12713888U JP H0249230 U JPH0249230 U JP H0249230U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- unlocked
- voltage
- means detects
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 9
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
第１図は本考案の完全同期検波回路の一実施例
を示したブロツク図、第２図は第１図に示した電
圧クランプ回路の詳細例を示した図、第３図は従
来の完全同期検波回路の一例を示したブロツク図
、第４図は従来の完全同期検波回路の他の例を示
したブロツク図である。
１…電圧制御発振器、２…移相器、３…位相検
波器、４…同期検波器、５…ＰＬＬロツク検出回
路、７…フイルタ回路、８…電圧クランプ回路。
Fig. 1 is a block diagram showing an embodiment of the fully synchronous detection circuit of the present invention, Fig. 2 is a diagram showing a detailed example of the voltage clamp circuit shown in Fig. 1, and Fig. 3 is a block diagram showing an example of the fully synchronous detection circuit of the present invention. A block diagram showing an example of a detection circuit. FIG. 4 is a block diagram showing another example of a conventional fully synchronous detection circuit. DESCRIPTION OF SYMBOLS 1... Voltage controlled oscillator, 2... Phase shifter, 3... Phase detector, 4... Synchronous detector, 5... PLL lock detection circuit, 7... Filter circuit, 8... Voltage clamp circuit.
Claims (1)
号を発振する電圧制御発振器に、前記第２の信号
を移相した信号と、前記第１の信号とを位相検波
器にて位相検波して得た検波電圧を帰還するＰＬ
Ｌ回路を備えた完全同期検波回路において、前記
ＰＬＬ回路のロツクがはずれたことを検出するロ
ツク検出手段と、このロツク検出手段によつて前
記ＰＬＬ回路のロツクがはずれたことが検出され
ると前記電圧制御発振器に帰還される前記検波電
圧を所定の値にクランプする電圧クランプ手段と
を具備したことを特徴とする完全同期検波回路。 A voltage controlled oscillator that oscillates a second signal completely synchronized with the first signal to be detected, and a phase detector that detects the phase of the second signal and the first signal. PL that feeds back the detected voltage obtained by
In a fully synchronous detection circuit including an L circuit, a lock detection means detects that the PLL circuit is unlocked, and when the lock detection means detects that the PLL circuit is unlocked, the lock detecting means detects that the PLL circuit is unlocked. 1. A fully synchronous detection circuit comprising voltage clamping means for clamping the detected voltage fed back to a voltage controlled oscillator to a predetermined value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12713888U JPH0249230U (en) | 1988-09-30 | 1988-09-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12713888U JPH0249230U (en) | 1988-09-30 | 1988-09-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0249230U true JPH0249230U (en) | 1990-04-05 |
Family
ID=31379292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12713888U Pending JPH0249230U (en) | 1988-09-30 | 1988-09-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0249230U (en) |
-
1988
- 1988-09-30 JP JP12713888U patent/JPH0249230U/ja active Pending
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