JPH0249595B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a solid-state imaging device that can provide high-definition images.

[Prior art and its problems]

Conventional television standard systems, such as the NTSC system, specify 512 vertical scanning lines, an interlaced scan frame with 2 fields, and a screen aspect ratio of 3:4. is configured to comply with this standard.

Currently, the number of pixels in, for example, an interline transfer type CCD (hereinafter referred to as IT-CCD) that conforms to this standard method is approximately 500 (vertical) x 400 (horizontal).

The imaging operation of such an IT-CCD will be briefly explained using FIG. In this IT-CCD, for example, a photodiode (hereinafter referred to as PD) is used.
2N×M photosensitive parts (for example, N=250, M=400)
P ₁₁ , P ₁₁ ′, P ₁₂ , P ₁₂ ′, P ₁₃ ,…, P _1N , P _1N ′,
P ₂₁ , P ₂₁ ′, P ₂₂ , P ₂₂ ′, P ₂₃ ,…, P _2N , P _2N ′,…,
P _M1 , P _M1 ′, P _M2 , P _M2 ′, P _M3 ,…, P _MN , P _MN ′,
(hereinafter represented by P _i , P _i ′) and this photosensitive area P _i ,
Vertical CCDs C ₁ , C ₂ , . . . , _CM for reading signal charges photoelectrically converted and accumulated by P _i ′ are arranged alternately in the horizontal direction. and vertical CCD
The signal charge is transferred to the horizontal CCD shift register 1 for each stage, and the horizontal
After being transferred within the CCD shift register 1, it is sequentially read out from the output section 2.

Here _, the number of transfer stages in _the vertical direction in the vertical _CCDs C ₁ , C ₂ , . In the standard television system, one frame consists of two fields, and interlace scanning is used. Therefore, the IT-CCD also performs imaging operations compatible with this, and the previous two fields are A,
It is divided into the B field, and the A field has two PDs P ₁₁ , P ₁₁ ′, which are continuously provided in the vertical direction.
P ₁₂ , P ₁₂ ′, P _1N , P _1N ′, P ₂₁ , P ₂₁ ′, P ₂₂ , P ₂₂ ′,
…, P _2N , P _2N ′,…, P _M1 ′, P _M1 ′, P _M2 , P _M2 ′,
…, P _MN , P _MN ′ are read out together, and in the B field, the signal charges are spatially perpendicular to the two PDs P _i , P _i ′ read out in the A field in the vertical direction. Two consecutive PDs with a phase difference of 180 degrees P ₁₁ ′, P ₁₂ , P ₁₂ ′, P ₁₃ , ..., P ₂₁ ′, P ₂₂ ,
The signal charges accumulated at P ₂₂ ′, P ₂₃ , ..., P _M1 ′, P _M2 , P _M2 ′, P _M3 , ... are read out together. Such signal charge readout mode is called field accumulation mode. In this case, the spatial phases of the signals read out in the A and B fields in the vertical direction differ by 180 degrees, so that 2N×M (= 500×
400) sample points are obtained.

Regarding the field accumulation mode, in the A field, PD(P ₁₁ , P ₁₂ , P ₁₃ , ..., P _1N ,
P ₂₁ , P ₂₂ , P ₂₃ ,…, P _2N ,…, P _M1 , P _M2 , P _M3 ,
…, P _MN ), and in the B field, every other PD P ₁₁ ′, P ₁₂ ′, P ₁₃ ′, ..., P _1N ′, P ₂₁ ′, P ₂₂ ′
，
P ₂₃ ′,…, P _2N ′,…, P _M1 ′, P _M2 ′, P _M3 ′,…,
There is a frame accumulation mode in which the signal charge of P _MN ' is read out.

Signal charge transfer from PD P _i , P _i ′ to vertical CCD C ₁ , C ₂ , ..., _CM is performed between PD P _i , P _i ′ and vertical CCD C ₁ ,
This is performed by applying a pulse voltage to a field shift gate (hereinafter referred to as FSG) 4 provided between C ₂ , . . . , _CM .

Recently, it has been considered to provide even higher definition images in television broadcasting using the above-mentioned standard system, with approximately 1000 vertical scanning lines and a screen aspect ratio of 3:5.

In order to adapt a solid-state imaging device to such a high-definition TV system, it must be able to output data corresponding to 1000 vertical scanning lines.

Therefore, in the above-mentioned IT-CCD,
At least the number of vertical transfer stages of the vertical CCDs C ₁ , C ₂ , ..., _CM is 500 stages, which is the same as the number of PD P _i , P _i ′ in the vertical direction, and the same PD P _i , P _i ′ is used in the A and B fields. By performing pseudo-interlace imaging in which accumulated signal charges are read out, it is possible to effectively achieve 1000 vertical scanning lines.

However, in IT-CCD, vertical
There are several problems in manufacturing when making the number of vertical transfer stages of CCD and the number of PDs in the vertical direction the same. This will be explained using FIG.

Figure 2a is a configuration diagram of the aforementioned IT-CCD viewed from the light irradiation side.
5-1,..., 5-i,... and vertical CCD channel 6
-1, 6-2, . . . are arranged alternately. Then, on the vertical CCD channels 6-1, 6-2, ..., first layer transfer electrodes 7-1, ..., 7-i, ... and second layer transfer electrodes 8-1, ..., 8- i,... are formed. The part 9 shown here by the dotted line
1, . . . , 9-i, . . . are overlapping portions of the first layer electrode and the second layer electrode.

FIG. 2b is a cross ^- sectional view taken along the line A-A' in FIG.
A gate oxide film 12 is formed on this N ⁺ layer 11,
Furthermore, the first layer transfer electrodes 7-1, 7-2, 7- are insulated from each other by an insulating layer 13.
3,... and second layer transfer electrodes 8-1, 8-2, 8
-3,... are formed by partially overlapping. One stage in this vertical CCD is composed of four electrodes, for example, transfer electrodes 7-1, 8-2, 7-
Corresponds to 2,8-3. and one PD5-i
Two transfer electrodes, e.g. 7-1, 8-2, in contact with
is located. In other words, the number of vertical transfer stages of the vertical CCD is 2PD pitch.

FIG. 2c is a sectional view taken along line BB' in FIG. 2a.
That is, PD (5-1,
..., 5-i, ... N ⁺ layers 14-1, 14-2,
Transfer electrodes 7-1, 7-2, 7 are formed between these N ⁺ layers.
-3, ..., 8-1, 8-2, 8-3, ... of the first layer transfer electrodes 7-1, 7-2, 7-, respectively continuous
3,... and second layer transfer electrodes 8-1, 8-2, 8-
3,... are formed overlapping each other with an insulating layer interposed therebetween. Furthermore, on the surface of the silicon substrate under these transfer electrodes, there are P ⁺ layers S ₁ , S ₂ , S ₃ , which are channel stoppers.
...is being formed.

In FIGS. 2a, b, and c, one pixel portion in the vertical direction is indicated by A _P , and the overlapping portion between the first layer electrode and the second layer electrode is indicated by A _O.

Note that after the structure shown in FIG. 2, there are steps such as forming an electrode for optically shielding the vertical CCD section and forming a passivation film, but these steps are omitted here.

However, as mentioned above, in order to realize an IT-CCD with this structure as a solid-state imaging device for high-definition TV, if we try to make the number of transfer stages of each vertical CCD and the number of PDs in the vertical direction the same, the above four Transfer electrodes 7-1, 8-2, 7-2, 8-3 are connected to one
This means that it must be formed in contact with the PD (that is, one pixel portion _AP ). In this case, even if high integration is possible with the structure shown in Figure b on the vertical CCD channels 6-1, 6-2,..., the first layer electrode and the second layer shown in Figure c Two overlapping portions A _O of the eye electrodes are required in one pixel portion A _P. As a result, the N ⁺ layers of PD 14-1, 14-2, 14-
3, 14-4, . . . due to the formation of the transfer electrodes, sensitivity deterioration occurs. On the other hand, if we try to form each transfer electrode in a separate layer to avoid this, four-layer electrodes will overlap on the overlapping part A _O ,
Due to electrode formation, disconnection of the upper electrode, a decrease in the photosensitive area caused by arranging the electrode in the overlapping portion in the middle of one pixel portion A _P , and a significant decrease in the smoothness of the substrate surface, etc. occur.

In this way, in order to make the number of vertical CCD transfer stages and the number of vertical PDs the same in order to improve the resolution of IT-CCDs, various problems arise such as deterioration of sensitivity, complication of structure, and deterioration of the smoothness of the substrate surface. It was hot.

[Purpose of the invention]

The present invention has been developed in view of the above points, and is a solid-state imaging device that allows the number of vertical CCD transfer stages and the number of vertical PDs to be the same without deterioration of sensitivity, complexity of structure, deterioration of substrate surface smoothness, etc. The purpose is to provide equipment.

[Summary of the invention]

In the solid-state imaging device according to the present invention, the first
The electrode of the first layer and the electrode of the second layer are stacked and arranged in the horizontal direction between the storage regions that accumulate signal charges, and in the vertical charge transfer element region adjacent to the storage region, the electrodes of the first layer and the electrodes of the second layer are stacked. Eliminate the overlap with the second layer electrode, and conversely form a gap between the first layer electrode and the second layer electrode, and cover the gap with the first layer and second layer electrode. A third layer that is insulated from the electrodes of the second layer is formed continuously in the vertical direction, and a pulse signal is applied to the electrodes of the first, second, and third layers to generate signal charges. The feature is that it performs transfer.

〔Effect of the invention〕

According to the present invention, vertical alignment can be achieved without reducing the area of the sensitive region, deteriorating the smoothness of the substrate surface, or increasing the structural complexity.
Since the number of CCD transfer stages and the number of vertical PDs can be made the same, a solid-state imaging device that can be adapted to high-definition TV systems can be achieved.

[Embodiments of the invention]

The present invention will be described in detail below with reference to the drawings.

FIG. 3 is a schematic diagram for explaining the imaging operation by the solid-state imaging device of the present invention.

M rows of photosensitive parts P ₁ , P ₂ ,..., P _M formed by photodiodes (PD) and M rows of vertical CCDs
C ₁ , C ₂ , ..., _CM are arranged alternately as shown in the figure,
Each row of photosensitive parts is P ₁₁ , P ₁₁ ′, P ₁₂ , P ₁₂ ′, P ₁₃ ′,...,
P _1N , P _1N ′, P ₂₁ , P ₂₁ ′, P ₂₂ , P ₂₂ ′, P ₂₃ ,…,
P _2N , P _2N ′,…, P _M1 , P _M1 ′, P _M2 , P _M2 ′, P _M3 ,
..., P _MN , P _MN ′ are arranged, and each vertical CCD has C ₁₁ , C ₁₁ ′, C ₁₂ , C ₁₂ ′, C in one-to-one correspondence with the PD. ₁₃ ，…，C _1N ，C _1N ′，
C ₂₁ , C ₂₁ ′, C ₂₂ , C ₂₂ ′, C ₂₃ ,…, C _2N , C _2N ′,…,
It has 2N transfer stages such as C _M1 , C _M1 ′, C _M2 , C _M2 ′, C _M3 , ..., C _MN , C _MN ′. That is, the photosensitive sections and the vertical CCDs are arranged alternately, and the number of transfer stages of the vertical CCDs and the number of PDs in the vertical direction are the same. Here N
For example, if 250, the vertical PD number and vertical
The number of CCD transfer stages is 500 in both cases.

In such a configuration, first, the signal charges accumulated in all PDs in the A field are simultaneously transferred to the vertical CCD via the FSG 4, and the vertical CCDs are transferred one stage at a time downward in the figure, and are transferred to the horizontal CCD shift register 1. The data is transferred to the left in the figure and read out from the output section 2. In the next B field, exactly the same operation as in the A field is performed. As a result, due to this pseudo-interlaced imaging, the actual number of pixels in the vertical direction becomes 1000.

Next, an embodiment of the structure of a solid-state imaging device according to the present invention that can have a planar structure as shown in FIG. 3 will be described with reference to FIG. 4.

FIG. 4a shows a structure according to the invention corresponding to FIG. 2a, in which the same parts as in FIG. 2a are designated by the same reference numerals.

In the horizontal direction, PD5-1, which is a photosensitive part,...
5-i, ... and vertical CCD channels 6-1, 6-2,
... are arranged alternately, and the first layer transfer electrodes 2 are placed on the vertical CCD channels 6-1, 6-2, ....
0-1,..., 20-i,... and the second layer transfer electrodes 21-1,..., 21-i,... are located in the gap portion 22-1,..., approximately in the middle of one pixel portion _AP . 22-i,...
It is formed with Then, on the transfer electrodes of the first layer and the second layer, the electrode 23-
1, 23-2, . . . are formed. Note that A _O indicates an overlapping portion between the first layer electrode and the second layer electrode.

FIG. 4b shows the first layer transfer electrode 20-1,
..., 20-i, ... and the second layer transfer electrode 21-
1, . . . , 21-i, . . . are enlarged views showing approximately one pixel portion taken out. The upper right diagonal line is the first layer transfer electrode 20-1, 20 seen from the light incidence side.
-2,..., the lower right diagonal line is the second layer transfer electrode 2
1-1, 21-2, . . . , the cross portions are overlapping portions.

Figure 4c is a sectional view taken along line A-A' in Figure 4a.
It is a figure shown corresponding to figure b. An N ⁺ layer 11, which is a buried channel, is provided on a P-type silicon substrate 10, and a gate oxide film 12 is formed on this N ⁺ layer 11. Then, on this gate oxide film 12, first layer transfer electrodes 20-1, 20-2, 20
-3,... are formed, and the first insulating film 13 is formed thereon.
The second layer transfer electrodes 21-1, 21-
2, . . . are formed having an overlapping portion A _O with the first layer electrode. Furthermore, a third layer electrode 23-1 is formed continuously thereon in the vertical direction with the second insulating film 24 interposed therebetween. Here, the third layer electrode 23-1 is the first layer electrode 20-1.
1, 20-2, 20-3, ... and the second layer electrode 2
1-1, 21-2, . . . are formed so as to cover the gate oxide film 12 in the non-overlapping portions, that is, in the above-mentioned gap portions.

And the first layer electrodes 20-1, 20-2, 2
0-3,...second layer electrodes 21-1, 21-2,
...and by applying independent three-phase clock pulse voltages to the third layer electrode 23-1, the three consecutive electrodes, for example, the first layer electrode 20-2, the second layer electrode 20-2,
The electrode 21-1 of the first layer, and the electrode 21 of the second layer
-1 and the adjacent first layer electrode 20-1 by the third layer electrode 23-1.
It constitutes one stage of CCD transfer unit.

Figure 4d is a cross-sectional view taken along line B-B' in Figure 4a;
It is a diagram shown in correspondence with Figure c. As is clear from this figure, in the B-B' cross section, the first layer electrodes 20-1, 20-2,
20-3,... and second layer electrodes 21-1, 21-
Only the overlap with 2, 21-3, . . . is sufficient.

As described above, according to the present invention, vertical
In the CCD section, the first layer transfer electrode and the second layer transfer electrode are overlapped with each other in one direction, and the first layer transfer electrode
A third layer electrode is provided continuously in the signal charge transfer direction of the vertical CCD, covering the gap between the second layer and the second layer.
In addition, first and second layer electrodes are provided on both sides of the signal accumulation region in succession to the first and second layer transfer electrodes, and a three-phase clock is applied to each of the first, second, and third electrodes. Since the signal charges are transferred by this method, the area of the photosensitive region is not reduced, and there is no problem of deterioration in the smoothness of the substrate surface due to the four-layer structure. Therefore, it has a simple structure and can be applied as a solid-state imaging device for high-definition TVs without deterioration in sensitivity.

FIG. 5 shows another embodiment of the present invention, where FIG. 5a shows a plane view and FIG. In this embodiment, the third layer of electrodes in FIG.
It can also be used as a field shift gate for moving to a channel.

That is, in FIG. 5a, the third layer electrode extension portions 25-1, 25- are provided between the vertical CCD channels 6-1, . . . and the PDs 5-1, 5-2, .
2, . . . are provided, and this extended portion is used as a field shift gate. In addition, in the same figure b, 26-1,
26-2,... are N ⁺ layers forming the PD, 27-1,
27-2,... are N ⁺ that constitute the vertical CCD channel
Layers 28-1, 28-2, . . . indicate a P ⁺ layer constituting a channel stop, 29 a gate oxide film, and 30 a P type region serving as a field shift gate region.

If configured as in this embodiment, even in an imaging chip compatible with a 2/3-inch optical system and having a length of one pixel A _P in the vertical direction of about 10 μm, a field shift gate area of about 3.3 μm in the vertical direction can be provided. Note that field shift is achieved by applying a positive voltage to the third layer electrode, and signal charge transfer is achieved by applying a negative voltage clock pulse to the first, second, and third layer electrodes. It is done by folding.

In the IT-CCD described above, the vertical CCD is normally optically shielded, but in the present invention, the third layer electrode is made of silicide such as molybdenum silicide (MoSi ₂ ), molybdenum (Mo), tungsten ( By forming the third layer with a conductive electrode such as W) or aluminum (Al), the third layer electrode can also be used as a light shielding film, and the structure can be made simpler. In this case, the third electrode material layer only needs to be formed of a conductive electrode whose surface does not transmit light, so it may be formed of a plurality of material layers instead of a single material layer.

Note that although the above description has been made using a P-type silicon substrate, an N-type or other semiconductor substrate may also be used.

The present invention can also be applied to a so-called two-story sensor in which photoelectric conversion is performed by a photoconductive film and signal charges are read by a reading scanning circuit using a Si single crystal substrate.

Further, the signal charges in the present invention are not limited to those generated by light, but may be generated by accelerated electrons, X-rays, etc., for example.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the imaging operation of a conventional IT-CCD, Figure 2a is a configuration diagram of the IT-CCD in Figure 1 seen from the light irradiation side, and Figure 2b is the same as in Figure 2a. A
-A' sectional view, Figure 2c is a BB' sectional view of Figure 2a, Figure 3 is a diagram for explaining the imaging operation of the IT-CCD according to the present invention, and Figure 4a is the invention IT-
A configuration diagram of an embodiment of the CCD as seen from the light irradiation side, Figure 4b is an enlarged view of a portion of Figure 4a, Figure 4c
is a cross-sectional view taken along line A-A' in FIG. 4a, FIG. 4d is a cross-sectional view taken along line B-B' in FIG. 4a, and FIG. , Figure 5b is the fifth
FIG. P ₁ , P ₂ ,..., P _M : Photosensitive part, C ₁ , C ₂ ,..., C _M :
Vertical CCD, 1: Water all CCD shift register, 2:
Output section, 4: Field shift gate, 20-
1,...,20-i,...: first layer transfer electrode, 2
1-1,..., 21-i,...: second layer transfer electrode, 22-1,..., 22-i,...: void, 23
-1, 23-2, ...: third layer transfer electrode,
A _P : 1 pixel area, A _O : Overlapping area.

Claims (1)

[Scope of Claims] 1. A row of regions for accumulating signal charges generated by irradiation with light, electrons, X-rays, etc. and a vertical charge transfer element adjacent to the accumulation regions for reading out the signal charges are provided on a semiconductor substrate. In the solid-state imaging device, a first layer electrode and a second layer electrode are successively stacked in the horizontal direction between the storage regions in the vertical direction, and the vertical charge transfer element The electrodes of the first layer and the second layer extend in the vertical direction and in opposite directions to each other in the section, and while the electrodes of the first layer and the second layer do not overlap, One of the accumulation regions and the first layer are covered by providing a third layer of electrode continuously in the vertical direction.
One stage of the charge transfer element consisting of second and third layer electrodes is formed adjacent to each other, and a three-phase clock signal is applied to the first, second and third layer electrodes. A solid-state imaging device characterized in that the signal charge is transferred by the vertical charge transfer element by applying a voltage to the vertical charge transfer element. 2. The signal charge accumulated in the accumulation region is transferred to the charge transfer element by applying a pulse voltage to the third layer electrode. solid-state imaging device. 3. The solid-state imaging device according to claim 1, wherein the third layer electrode is formed of a conductive material layer that does not transmit light.