JPH0251465U - - Google Patents

Description

[Brief explanation of drawings]

1 to 13 show one embodiment of this invention, and each figure represents the following. Fig. 1 is a side structural diagram of the digital electronic copying device, Fig. 2 is a sectional view of Fig. 1, Fig. 3 is an explanatory diagram of the structure of the document table, and Fig. 4 is a configuration block diagram of the signal processing unit. , Fig. 5 is a block diagram of the sampling timing generation circuit for enlarged images and the threshold level generation section, Fig. 6 is a write/read circuit diagram for normal and mirror images, and Fig. 7 is a sampling clock for reduction. Figure 8 is a circuit diagram for central printing control (in the case of normal image), Figure 9 is a strobe generation circuit diagram, Figure 10 is a block diagram of the strobe width monitoring section,
FIG. 11 is a perspective view of the thermal head, FIG. 12 is a configuration diagram of the thermal head, FIG. 13A is an explanatory diagram showing the overlap of recording pixels when reducing in the sub-scanning direction without strobe width control, and FIG. B is an explanatory diagram showing the operation of recording pixels when strobe width is controlled in response to sub-scanning feed.

Claims (1)

[Claims for Utility Model Registration] A threshold level generation circuit for comparing an output waveform from an image sensor, and a threshold level generated from this circuit for comparing and encoding the output waveform. , in an image processing circuit having a comparison circuit, in order to obtain an N/M-times image signal, the same frequency divider circuit, an M-times frequency divider circuit, and N−M times in M times from the M-times frequency divider circuit are used. A timing pulse generation circuit for N/M times enlargement, which is composed of a switching circuit that switches to an equal frequency divider circuit; a sample hold circuit that holds the output waveform from the image sensor; An image characterized in that it is provided with a dither generation register that rotates a dither matrix, and a D/A conversion circuit that adds output signals from the dither generation register to synthesize the threshold level. processing circuit.