JPH0252898B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a multi-terminal information serial transmission system for transmitting information from multiple terminals at the same time for power system protection.

[Prior art]

A conventional device of this type is shown in FIG. In the figure, 1, 2, 2', 3 are information transmission devices, 4 is an input circuit of the information transmission devices 1, 2, 2',
5 is an output circuit of the information transmission devices 2, 2', and 3; 6 is a transmission line; 7 is a transmission line input terminal; and 8 is a transmission line output terminal. FIG. 2 is a detailed internal block diagram of the information transmission device 2, in which 9 is a decoder, 10 and 12 are shift registers for the data section, 11 and 13 are shift registers for the address section, 14 is a transmission encoder, and 15 is a shift register for the address section. A first shift register consisting of shift registers 10 and 11; 16 a second shift register consisting of shift registers 12 and 13; 17 decoding the address information of the first shift register and sample-holding when specific address information A sample-and-hold signal generator for transmitting signals, 18 a sample-and-hold signal output terminal (from now on, the abbreviation S/H will be used to mean sample-and-hold), 19 an address bus, 20 a data bus, and 21 a shift register 1.
5, 16 and the S/H signal generator 17.

Next, FIGS. 3 and 4 show the information transmission device 1,
This is a time chart illustrating the operation of a transmission system consisting of 2, 2', and 3. In the figure, A, B,
C, D, and I indicate the distance positions of the information transmission devices connected in series, and the rows of squares indicate the temporal flow of information in each device. Further, the numbers above the rows of squares indicate the temporal position of the same information in each row, and the numbers inside the squares indicate the names (addresses) given to each piece of information. Furthermore, lowercase letters a, b, c, d,
i indicates address information to be detected by the S/H signal generator 17 of each device at time t=T.
Note that FIG. 3 shows a state in which the transmission device C is in constant operation, and FIG. 4 shows a state in which the transmission device C has dropped out of the transmission system for some reason.

Next, the operation will be explained. First, the transmission device B shown in FIG. 3 will be explained along with FIG. 2.

The information input from the transmission line input terminal 7 is sent to the decoder 9.
The signal becomes a bit signal and is input to the first shift register 15 one bit at a time. This signal continues to be sent to the second shift register 16, and the output of the second shift register passes through the transmission encoder 14 and is sent from the transmission line output terminal 8. The length of the shift registers 15 and 16 is exactly one information unit (referred to as a word), and according to the word structure, the shift register 1 for the address section
0, 12 and data section shift registers 11, 13
It consists of a series circuit. shift register 1
When the words 5 and 16 are aligned, the controller 21 outputs or inputs addresses and data to the address bus 19 and data bus 20, thereby performing a certain process (the equipment for processing is the address bus, data bus 20, etc.). connected to the bus, but not shown; the same applies hereafter). Note that the address indicates whether or not the device should execute the process, that is, indicates the nature of the data.

Now, in transmission device B, address 19,
That is, when the word indicated by the symbol b is aligned in the first shift register and output onto the address bus,
The S/H signal generator 17 decodes it, and as shown in FIG.
Transmit the S/H signal at the time marked. Here, the transmission delay from the transmission line input terminal 7 to the transmission line output terminal 8 of the transmission device B is equivalent to two words because two shift registers for one word are connected in series as described above. This situation is shown in FIG.

On the other hand, since the purpose of this information transmission system is to transmit information at the same time t=T, the transmission device uses the S/H signal generator 1 as shown in FIG.
The addresses to be decoded for 7 are a, b, c, d,...i
It changes by two addresses like this.

By the way, in such a transmission system, if one of the transmission devices, for example transmission device C, has a problem and becomes unable to transmit, the transmission operation of the entire system will stop. Even in such cases, various measures are generally taken to prevent the entire transmission system from going down. For example, in optical transmission, a bypass using an optical switch is used.

However, in this case, the bypass prevents it from passing through the shift register for one transmission device, so
The data after the bypass will be two addresses earlier in time. FIG. 4 shows this state. As is clear from Figure 4, in a transmission device where words arrive faster, the address to be decoded (4th
In the figure, d, i) also arrive early, that is, the transmission device D,
In I, the S/H signal will be output at time t=T'.

Therefore, in conventional transmission systems, backup is difficult in the event of a failure in the transmission equipment, and even if measures such as bypass are taken, the simultaneity of signal transmission cannot be maintained due to this. There were flaws.

[Summary of the invention]

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and by adding a fixed number (2 words) to the sending address at the time of sending, S/ An object of the present invention is to provide an information transmission device that can ensure the same timing of H signals.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 5, 22 is an adder circuit, 23 is a timing control controller, and the rest is the same as the conventional example shown in FIG. 6 and 7 are time charts showing the operation of this embodiment; FIG. 6 shows a state in which it is in constant operation, and FIG. 7 shows a state in which the transmission device C has dropped out of the transmission system for some reason.

The numbering system in the figure is the same as in Figures 3 and 4, and the lowercase letters a', b', c', d', and i' indicate time t=
T
The address information to be detected by the S/H signal generator 17 of each device in is shown.

Next, the operation will be explained. To explain what happens after the words are lined up in the second shift register 16, the address information is transferred to the adder circuit 22 at the moment the words are lined up in the second shift register 16.
The information is replaced with information obtained by adding two addresses, and address transmission by the second shift register 16 begins. Therefore, as shown in FIG.
The addresses of B, C, D, and I at the same time all match. That is, the data is delayed by two addresses as in the conventional device, but only the address names are kept the same in time. Therefore, transmission is performed by keeping the addresses of all transmission devices A to I the same (21 in this case).

Next, if transmission device C is dropped, as shown in Figure 7, the transmission delay due to the shift register of transmission device C will be eliminated, but at the same time, the address addition operation will also be eliminated, so the time delay of the address name will also be eliminated. Identity is maintained. Therefore, even if the transmission device is dropped, the same timing of S/H signal generation is ensured. In this case, as described above, the address names to be decoded by each transmission device match, and therefore there is no restriction on the order of the transmission devices.

Furthermore, the same effect as above can be obtained when a transmission device is added.

In the above embodiment, the S/H signal generator decodes the address of the first shift register, but it may decode the address of the second shift register. Also, as an adder format, after reading the address of the second shift register and adding it,
However, the present invention is not limited to the type or method of the adder. That is, the address of the first shift register may be temporarily stored and the addition address may be input to the second shift register two words later, or a serial addition circuit (adding one bit at a time when transmitting an address) may be used. You may also use it.

Further, in the above embodiment, a transmission device having a two-word shift register has been described, but the same effect can be achieved even if the present invention is implemented in a transmission device having a shift register consisting of many words or a one-word shift register. In this case, the number of additions is the number of word-based shift registers.

〔Effect of the invention〕

As described above, according to the present invention, a fixed number is added to the transmission address at the time of transmission, so even if a transmission device is dropped or added, the same timing of the S/H signal is maintained, and the information reliability is improved. This has the advantage that a device with high performance can be obtained at low cost.

[Brief explanation of the drawing]

Fig. 1 is a conceptual diagram of a serial transmission system, Fig. 2 is a block diagram of a conventional transmission device, Figs. 3 and 4 are time charts for explaining operation, and Fig. 5 shows an embodiment of the present invention. Block diagrams, Figures 6 and 7 are shown in Figure 5.
3 is a time chart showing the operation of the embodiment shown in the figure. 1, 2, 2', 3... Information transmission device, 6 is a transmission line, 15, 16... Shift register, 11, 13
... Address section shift register, 17 ... Sample and hold signal generator, 19 ... Address bus,
20...data bus, 22...addition circuit.

Claims (1)

[Claims] 1 Consisting of a plurality of transmission devices including first and second serially connected shift registers that sequentially accommodate a serial signal for one information unit consisting of a data part and an address part, and two information units in series, each transmission device The timing of parallel access to these first and second shift registers is determined by decoding the address part of the serial signal that is sequentially stored in the first and second shift registers and sent out. In a transmission system in which data is transmitted and received, each transmission device is provided with means for adding a predetermined constant value to the address part of the serial signal sent out from the second shift register, and each transmission device 1. A multi-terminal information serial transmission system characterized in that the contents of address parts of serial signals to be decoded are all the same.