JPH0253290U - - Google Patents
Info
- Publication number
- JPH0253290U JPH0253290U JP1988130415U JP13041588U JPH0253290U JP H0253290 U JPH0253290 U JP H0253290U JP 1988130415 U JP1988130415 U JP 1988130415U JP 13041588 U JP13041588 U JP 13041588U JP H0253290 U JPH0253290 U JP H0253290U
- Authority
- JP
- Japan
- Prior art keywords
- pwm
- servo controller
- pwm pulse
- servo
- parallel data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 10
Landscapes
- Control Of Direct Current Motors (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
第１図の各部波形図、第３図はサーボドライバの
構成図、第４図はサーボコントローラの内部構成
図、第５図は第４図の詳細図、第６図は第５図に
示すパラレルデータ変換部を主に示す回路図、第
７図は第６図の各部波形図、第８図ａ，ｂ，ｃは
ＰＷＭパルス発生の説明図、第９図はノイズの説
明図、第１０図はノイズ重畳の場合の波形図であ
る。
図中、１０１は分周器、１０２，１０３，１０
４，１０８はＤＦＦ、１０５はバイナリカウンタ
、１０６はラツチ、１０９はＡＮＤゲートである
。
Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2 is a waveform diagram of each part of Figure 1, Figure 3 is a configuration diagram of a servo driver, Figure 4 is an internal configuration diagram of a servo controller, and Figure 5. is a detailed diagram of Fig. 4, Fig. 6 is a circuit diagram mainly showing the parallel data conversion section shown in Fig. 5, Fig. 7 is a waveform diagram of each part of Fig. 6, and Fig. 8 a, b, and c are PWM FIG. 9 is an explanatory diagram of pulse generation, FIG. 9 is an explanatory diagram of noise, and FIG. 10 is a waveform diagram in the case of noise superimposition. In the figure, 101 is a frequency divider, 102, 103, 10
4, 108 is a DFF, 105 is a binary counter, 106 is a latch, and 109 is an AND gate.
Claims (1)
ＰＷＭ変換部を有してサーボコントローラに戻る
系を有するサーボドライバにおいて、 上記サーボコントローラ内のうちＰＷＭパルス
を受けてパラレルデータに変換するパラレルデー
タ変換部にあつて、上記ＰＷＭパルスの立上りと
クロツクを分周して得た同期信号区間にて立上り
上記ＰＷＭパルスの立下りにて立下るカウンタへ
のカウント信号と上記ＰＷＭパルスの立上りとの
アンドを採り、データのラツチやＰＩ演算の開始
を行なうことを特徴とするＤＣモータの速度制御
サーボドライバ。[Scope of Claim for Utility Model Registration] In a servo driver that has a PWM converter in the feedback loop from the DC motor side and a system that returns to the servo controller, the servo controller receives PWM pulses and receives parallel data from the servo controller. In the parallel data conversion unit, a count signal to the counter that rises at the rise of the PWM pulse and a synchronization signal obtained by dividing the clock, and falls at the fall of the PWM pulse, and the PWM pulse. A speed control servo driver for a DC motor, characterized in that it performs an AND with the rising edge of , and latches data and starts PI calculation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988130415U JPH0753436Y2 (en) | 1988-10-06 | 1988-10-06 | DC motor speed control servo driver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988130415U JPH0753436Y2 (en) | 1988-10-06 | 1988-10-06 | DC motor speed control servo driver |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0253290U true JPH0253290U (en) | 1990-04-17 |
| JPH0753436Y2 JPH0753436Y2 (en) | 1995-12-06 |
Family
ID=31385562
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988130415U Expired - Lifetime JPH0753436Y2 (en) | 1988-10-06 | 1988-10-06 | DC motor speed control servo driver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0753436Y2 (en) |
-
1988
- 1988-10-06 JP JP1988130415U patent/JPH0753436Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0753436Y2 (en) | 1995-12-06 |
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