JPH025334B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sawtooth wave generation circuit, and more particularly to a sawtooth wave generation circuit suitable for use in a vertical deflection circuit of a television receiver.

This type of sawtooth wave generation circuit consists of a synchronous oscillation circuit section whose oscillation is synchronized by a trigger pulse, and a sawtooth wave generation circuit which generates a sawtooth wave signal in response to the oscillation signal from this circuit section. Consists of. The synchronous oscillation circuit section is required to have low temperature dependence and power supply voltage dependence of the oscillation signal, and the sawtooth wave generation section is required to have stability in the peak value of the generated sawtooth wave signal. Further, it is desirable that the configuration be suitable for integration into an integrated circuit.

Therefore, an object of the present invention is to provide an integrated circuit that can satisfy such requirements, that is, the temperature dependence and power supply voltage dependence of the signal to be generated are small, and the peak value of the signal is stable. The purpose of the present invention is to provide a sawtooth wave generation circuit suitable for.

The sawtooth wave generating circuit according to the present invention has first and second transistors connected in a differential manner, and takes a first output state when the first transistor is conductive and outputs the second output state. a differential amplifier that assumes a second output state when the transistor is conductive; means for supplying a reference voltage to the first transistor; and a differential amplifier that assumes a second output state when the transistor is conductive; and a third transistor that is in a cutoff state in response to the second output state, and a voltage generating means that includes a diode and is provided between the third transistor and the reference terminal, and the third transistor a voltage generating means for generating first and second bias voltages and a third bias voltage including a voltage drop across the diode in response to a current in a conducting state; a fourth transistor connected between one end and the power supply terminal and conductive in response to the first bias voltage; and a fourth transistor connected between the other end of the capacitor and the reference terminal and responsive to the second bias voltage. a charging circuit that charges the capacitor, the charging circuit having a fifth transistor that conducts and conducts; a first resistor connected between the other end of the capacitor and the power supply terminal; a discharge circuit for discharging the capacitor and having a second resistor connected between the terminal and the capacitor; means for supplying the charging voltage of the capacitor to the second transistor; and means for applying a trigger pulse to the capacitor. a sixth transistor that conducts and generates a drive current in response to the third bias voltage from the voltage generating means; a second capacitor; A switching circuit for controlling charging and discharging of the second capacitor is provided, and a sawtooth wave signal is obtained from the second capacitor.

Hereinafter, the present invention will be explained in detail with reference to the accompanying drawings.

FIG. 1 shows an embodiment of the present invention, and the portion surrounded by dotted lines constitutes an oscillation circuit. A load resistor 10 is connected to the collector side of the transistor 11 of the transistors 11 and 12 connected in a differential manner for switching the charging of the capacitor 3 and determining its reference potential, thereby biasing the switching transistor 7. Further, on the collector side of the transistor 7, there are resistors 9, 209, 210 for biasing the transistors 4 and 6 forming the charging circuit.
and diode 211 are connected. Furthermore, a resistor 5 is connected to the collector side of the transistor 6 for the charging path to determine the charging time constant. Further, a variable resistor 1 is connected between the connection point b between the capacitor 3 and the resistor 5 and the power supply _Vcc , while a resistor 2 is connected between the connection point a between the capacitor 3 and the emitter of the transistor 4 and the ground. It forms a discharge path.

The oscillation frequency is varied by changing the charging time constant of the capacitor 3 using the variable resistor 1. or,
The reference potential for switching charging and discharging of the capacitor 3 is given by the base potential of the transistor 12, that is, the voltage obtained by dividing the power supply voltage by the resistors 14 and 15.

A special feature of the oscillation circuit shown in FIG. 1 will be explained in detail based on FIG. 2. First, consider the charging section for the capacitor 3. Here, the on/off states of the transistors 11 and 12 connected in a differential manner are reversed when the base bias of the transistor 12 is set as a reference potential and the base potential of the transistor 11 becomes equal to or higher than the reference potential.
are turned on and off, respectively, and when the potential is lower than the reference potential, transistors 11 and 12 are turned off and on, respectively. Therefore, in FIG. 2, due to the discharge of capacitor 3, transistor 1
When the base potential of transistor 1 rises and reaches the reference potential E ₀ , the transistor 1 connected in a differential manner instantly
The on and off states of transistors 1 and 12 are reversed, and transistors 11 and 12 are turned on and off, respectively.
As a result, transistor 7 is biased by resistor 10 and turned on at the same time, and transistors 4 and 6 are also biased by resistors 9, 209, 210 and diode 211 and turned on. Therefore, capacitor 3 is power supply → transistor 4 → capacitor 3 → resistor 5 → transistor 6
→A charging path is formed along the ground path and charging begins. At this time, the base potential of the transistor 11 rises to the power supply voltage _Vcc , considering for convenience the moment when the charge on the capacitor 3 becomes zero.

Therefore, if the charging start voltage to the capacitor 3 is E ₁ , then E ₁ =V _cc .

The charging time constant τ ₁ for capacitor 3 is τ ₁ = C ₃ R ₅
is given by

Further, the charging time T ₁ is given by the following equation.

T ₁ = C ₃ R ₅ 1nE ₁ /E ₀ However, E ₀ = R ₁₅ /R ₁₄ + R ₁₅ V _cc , E ₁ = Vc.c. Therefore, T ₁ =C ₃ R ₅ 1nR ₁₄ +R ₁₅ /R ₁₅ (1) Next, consider the charging section for the capacitor 3.
When the base potential of the transistor 11 reaches the reference potential E ₀ after the charging time T ₁ described above, the relationship between the on and off states of the transistors 11 and 12 connected in a differential manner is instantaneously reversed, and the transistor 11 is in the off state. 12 is in the on state. Therefore, transistors 4, 6, and 7 are all cut off, and capacitor 3 is completely cut off from the charging path, while capacitor 3 (point b) → variable resistor 1 → power supply → ground → resistor 2 → capacitor 3 (point a) ) a discharge path is formed. Therefore, the discharge of the capacitor 3 starts immediately after the transistor 11 is turned off, but at this time, since the point a is connected to the ground point by the resistor 2, the reference potential becomes the ground potential, and the capacitor 3 is charged. Since the point a side becomes a positive potential depending on the direction, the point b, that is, the base potential of the transistor 11, instantly drops to _E2 .

However, in this case, the shift from ground to _-E2 potential is equal to the charge charged in capacitor 3 -
E ₂ = V _cc −E ₀ .

The charging time constant τ ₂ is determined by τ ₂ =C ₃ (R ₁ +R ₂ ).

The charging time T ₂ is given by the following equation.

T ₂ = C ₃ (R ₁ + R ₂ )1n2V _cc −E ₀ /V _cc −E ₀ …(2) However, E ₀ = R ₁₅ /R ₁₄ +R ₁₅ V As the charging of _cc capacitor 3 progresses, formula (2) is obtained. time shown
After T ₂ , when the base potential of the transistor 11 reaches the reference potential E ₀ , the transistor 11 is turned on and charging starts again. Due to the above relationship, oscillation continues, but the oscillation period T is the sum of the charging time T ₁ and the discharging time T ₂ , and therefore the oscillation frequency is f
It can be expressed as = 1/(T ₁ + T ₂ ). As can be seen from equations (1) and (2), T is unrelated to V _cc and is
Since the relationship is the ratio of R ₁₄ and R ₁₅ , a stable oscillation circuit is created that is free from dependence on power supply voltage and influence from the absolute value of resistance.

The circuit shown in Figure 1 is a sawtooth wave generation circuit for the vertical deflection circuit of a television receiver, and in addition to the above-mentioned oscillation circuit, a sawtooth wave generation circuit section and a vertical synchronization separation circuit are added. . That is, the sawtooth wave generating section includes a capacitor 225 and a resistor 226.
a switching circuit connected in parallel to a capacitor 225 and consisting of transistors 221 to 224 and resistors 220 and 222;
It has a transistor 218 that drives this circuit. 219 is an emitter resistance of the transistor 218. The transistor 218 is made conductive by the bias voltage taken out from the anode side of the diode 211, and supplies a drive current to the switching circuit. Therefore, the transistor 218 operates as a constant current source only during the charging period of the capacitor 3, and drives the switching circuit with the constant current. Therefore, a sawtooth wave signal with a stable peak value can be obtained from the sawtooth wave generation capacitor 225.

In order to completely match the frequency of the sawtooth wave to the vertical synchronization frequency, it is necessary to control the above-mentioned oscillation by the vertical synchronization frequency signal. The application point of the synchronization trigger pulse may be point a, and when the oscillation frequency is less than the repetition frequency of the trigger pulse, that is, the vertical synchronization frequency, the frequency is pulled in and the oscillation circuit performs synchronized oscillation.

Generally, the trigger pulse is sent to an integrator circuit 20 made up of a capacitor and a resistor, rather than a synchronization signal separation circuit.
1 is further applied via a coupling capacitor 202. In the present invention, since the oscillation capacitor 3 is floating above the power supply or ground point, two connection terminals are required when integration is taken into consideration, but since the trigger pulse application point can be shared with one terminal of the capacitor. , the number of terminals can be reduced.

The lower limit frequency for synchronous pull-in of the oscillation frequency when a trigger pulse is applied is determined by the amplitude of the trigger pulse relative to the oscillation waveform amplitude defined by E ₀ and E ₂ in Figure 2, and furthermore, in this application, the constant of resistor 2 is determined by By changing the input impedance of the trigger pulse application point a, the lower limit frequency of synchronization pull-in can be adjusted. Furthermore, if one end of the synchronizing signal source is connected to the reference potential point through a resistor, the coupling capacitor 202 may not be used.

As described above, it is possible to obtain a sawtooth wave synchronized with the vertical synchronization frequency, which is further guided to the deflection yoke amplified by the vertical output stage through amplitude adjustment and linearity adjustment.

Although the resistor 204 is directly grounded to the reference potential point in FIG. 1, it may be connected to the bias power supply 118 as shown in FIG. In this case, the oscillation type amplitude is such that the charging start voltage _E1 is lowered to below the power supply voltage _Vcc at the emitter potential of the transistor 4,
Furthermore, since the discharge starting voltage E ₂ is also raised above the ground potential by the bias power supply 118,
As shown in FIG. 4, it is possible to make the oscillation waveform amplitude smaller than that in the embodiment shown in FIG.
Therefore, transistor 6 eliminates the influence of parasitic transistors and the problem of reverse breakdown voltage between the base and emitter of transistor 11. It should be noted that FIG. 3 shows only the oscillation circuit portion, and the same functional parts as in FIG. 1 are designated by the same numbers and their explanation will be omitted.

The effect that the base-emitter forward voltage of the transistors 4, 6 and diode 211 shown in FIGS. 1 and 3 have on the oscillation frequency is
It can be canceled by appropriate settings of 09, 210, 14, and 15.

FIG. 5 shows an oscillation circuit according to still another embodiment of the present invention, which is characterized in that a resistor 305 is inserted on the collector side of transistor 4 forming a charging path, and transistor 4 is used in a saturated state. Since the transistor 7 is driven at a constant current by the diodes 309, 315 and the resistor 308, and fluctuations in the base potential of the transistor 4 are suppressed, the temperature dependence of the oscillation frequency is extremely good.

Furthermore, it is also possible to make the oscillation frequency drop in response to a drop in power supply voltage that exceeds a predetermined operating range. Considering the way the screen appears as a circuit, it is convenient because the screen can be displayed in a synchronous retracted state.

As described above, the present invention is extremely easy to apply to integrated circuits, has a simple circuit configuration, and can construct an oscillator with excellent performance and low voltage dependence and temperature dependence of the oscillation frequency.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention, FIG. 2 is an oscillation waveform diagram in the oscillation circuit of FIG. 1, and FIG. 3 is a circuit diagram showing another embodiment of the oscillation circuit according to the present invention. , FIG. 4 is an oscillation waveform diagram of FIG. 3, and FIG. 5 is a wiring diagram showing still another embodiment of the oscillation circuit according to the present invention. 1, 2, 5, 9, 10, 13, 14, 15, 2
09,210,220,222,226...Resistor, 3,225...Capacitor, 4,6,7,1
1, 12, 218, 221, 223, 224...
transistor.

Claims (1)

[Claims] 1 having first and second transistors connected in a differential manner, having a first output state when the first transistor is conductive and a second output state when the second transistor is conductive; means for supplying a reference voltage to the first transistor; and a means for supplying a reference voltage to the first transistor, which becomes conductive in response to the first output state of the differential amplifier and responds to the second output state. a third transistor that is in a cut-off state when the transistor is turned off; a third bias voltage including the first and second bias voltages and a voltage drop across the diode in response;
a first capacitor; a fourth transistor connected between one end of the capacitor and a power supply terminal and conductive in response to the first bias voltage; and the capacitor. a charging circuit that charges the capacitor and includes a fifth transistor that is connected between the other end of the capacitor and the reference terminal and conducts in response to the second bias voltage; and the other end of the capacitor and the power source. a discharge circuit for discharging the capacitor, the circuit having a first resistor connected to a terminal and a second resistor connected between the one end of the capacitor and the reference voltage; and charging and discharging the capacitor. means for supplying a voltage to the second transistor; and means for applying a trigger pulse to the capacitor;
a sixth transistor that conducts and generates a drive current in response to the third bias voltage from the voltage generating means, a second capacitor, and the second transistor in response to the drive current from the fifth transistor; a switching circuit for controlling charging and discharging of the second capacitor, and obtaining a sawtooth wave signal from the second capacitor.