JPH0253629U - - Google Patents

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Publication number
JPH0253629U
JPH0253629U JP13136788U JP13136788U JPH0253629U JP H0253629 U JPH0253629 U JP H0253629U JP 13136788 U JP13136788 U JP 13136788U JP 13136788 U JP13136788 U JP 13136788U JP H0253629 U JPH0253629 U JP H0253629U
Authority
JP
Japan
Prior art keywords
input
circuit
capacitors
amplifier
differential amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13136788U
Other languages
Japanese (ja)
Other versions
JPH0540576Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988131367U priority Critical patent/JPH0540576Y2/ja
Publication of JPH0253629U publication Critical patent/JPH0253629U/ja
Application granted granted Critical
Publication of JPH0540576Y2 publication Critical patent/JPH0540576Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Networks Using Active Elements (AREA)
  • Amplifiers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図乃至第4図はこの考案に係る低周波増幅
器の入力回路の実施例を示し、第1図は低周波増
幅器として例えば音響増幅器のフオノイコライザ
回路を示した回路図、第2図はこの音響増幅器の
動作を説明するための回路図、第3図は入力イン
ピーダンスの周波数特性を示した特性図、第4図
は他の実施例を示した低周波増幅器の回路図であ
る。第5図は従来例の低周波増幅器の回路図であ
る。 主な符号の説明、1:入力端子、2:出力端子
、3:RIAA回路、4:演算増幅器、10:こ
の考案の増幅器の特性曲線、11:従来例の増幅
器の特性曲線、20:他の実施例の差動増幅器、
Q1,Q2:差動増幅器。
1 to 4 show an embodiment of the input circuit of a low frequency amplifier according to this invention, FIG. 1 is a circuit diagram showing a phono equalizer circuit of an acoustic amplifier as a low frequency amplifier, and FIG. 2 is a circuit diagram of this example. FIG. 3 is a circuit diagram for explaining the operation of the acoustic amplifier, FIG. 3 is a characteristic diagram showing the frequency characteristics of input impedance, and FIG. 4 is a circuit diagram of a low frequency amplifier showing another embodiment. FIG. 5 is a circuit diagram of a conventional low frequency amplifier. Explanation of main symbols, 1: Input terminal, 2: Output terminal, 3: RIAA circuit, 4: Operational amplifier, 10: Characteristic curve of the amplifier of this invention, 11: Characteristic curve of the conventional amplifier, 20: Other Example differential amplifier,
Q 1 , Q 2 : Differential amplifier.

Claims (1)

【実用新案登録請求の範囲】 1 差動増幅器の入力回路に第1及び第2のコン
デンサとインダクタンスを用いた入力フイルタ回
路を形成して、高周波妨害電流を排除した低周波
増幅器の入力回路において、 上記入力フイルタ回路の第2のコンデンサを直
列接続した第3及び第4のコンデンサに置換し、
この第3及び第4のコンデンサの直列接続の一端
を差動増幅器の非反転入力に接続し、他の一端を
接地するとともに、この第3及び第4のコンデン
サの直列接続の中点より抵抗を介して差動増幅器
の反転入力に接続して構成したことを特徴とする
低周波増幅器の入力回路。 2 上記入力フイルタ回路のインダクタンスの代
りに抵抗を用い、更に差動増幅器の非反転入力と
反転入力間に第5のコンデンサを接続して構成し
たことを特徴とする請求項1記載の低周波増幅器
の入力回路。
[Claims for Utility Model Registration] 1. In the input circuit of a low frequency amplifier in which high frequency interference current is eliminated by forming an input filter circuit using first and second capacitors and inductance in the input circuit of the differential amplifier, replacing the second capacitor of the input filter circuit with third and fourth capacitors connected in series,
One end of the series connection of the third and fourth capacitors is connected to the non-inverting input of the differential amplifier, the other end is grounded, and a resistor is connected from the midpoint of the series connection of the third and fourth capacitors. An input circuit for a low frequency amplifier, characterized in that the input circuit is connected to an inverting input of a differential amplifier through the inverting input circuit. 2. The low frequency amplifier according to claim 1, wherein a resistor is used in place of the inductance of the input filter circuit, and a fifth capacitor is further connected between the non-inverting input and the inverting input of the differential amplifier. input circuit.
JP1988131367U 1988-10-08 1988-10-08 Expired - Lifetime JPH0540576Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988131367U JPH0540576Y2 (en) 1988-10-08 1988-10-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988131367U JPH0540576Y2 (en) 1988-10-08 1988-10-08

Publications (2)

Publication Number Publication Date
JPH0253629U true JPH0253629U (en) 1990-04-18
JPH0540576Y2 JPH0540576Y2 (en) 1993-10-14

Family

ID=31387367

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988131367U Expired - Lifetime JPH0540576Y2 (en) 1988-10-08 1988-10-08

Country Status (1)

Country Link
JP (1) JPH0540576Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023074039A (en) * 2021-11-17 2023-05-29 エイブリック株式会社 integration circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51145836U (en) * 1975-05-17 1976-11-24
JPS6173497A (en) * 1984-09-19 1986-04-15 Matsushita Electric Ind Co Ltd Equalizer amplifier input circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51145836U (en) * 1975-05-17 1976-11-24
JPS6173497A (en) * 1984-09-19 1986-04-15 Matsushita Electric Ind Co Ltd Equalizer amplifier input circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023074039A (en) * 2021-11-17 2023-05-29 エイブリック株式会社 integration circuit

Also Published As

Publication number Publication date
JPH0540576Y2 (en) 1993-10-14

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