JPH0254242U - - Google Patents
Info
- Publication number
- JPH0254242U JPH0254242U JP1988134063U JP13406388U JPH0254242U JP H0254242 U JPH0254242 U JP H0254242U JP 1988134063 U JP1988134063 U JP 1988134063U JP 13406388 U JP13406388 U JP 13406388U JP H0254242 U JPH0254242 U JP H0254242U
- Authority
- JP
- Japan
- Prior art keywords
- point
- symmetrical
- diode chip
- symmetrical part
- diode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の一実施例の平面図、第２図は
第１図の等価回路図、第３図及び第４図は従来の
ミキサダイオードの一例の平面図及びＡ―Ａ′線
断面図、第５図は第３図の等価回路図である。 １……ダイオードチツプ、２……アイランド、
ｌ１〜ｌ４……第１〜第４のボンデイングワイヤ
。
第１図の等価回路図、第３図及び第４図は従来の
ミキサダイオードの一例の平面図及びＡ―Ａ′線
断面図、第５図は第３図の等価回路図である。 １……ダイオードチツプ、２……アイランド、
ｌ１〜ｌ４……第１〜第４のボンデイングワイヤ
。
Claims (1)
- ダイオードチツプを点対称部に載置する点対称
形状のアイランドと、前記点対称部に対して点対
称に配置されかつ前記ダイオードチツプに同一長
のボンデイングワイヤを介して接続する複数のリ
ードとを含むことを特徴とするミキサダイオード
。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988134063U JPH0254242U (ja) | 1988-10-13 | 1988-10-13 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988134063U JPH0254242U (ja) | 1988-10-13 | 1988-10-13 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0254242U true JPH0254242U (ja) | 1990-04-19 |
Family
ID=31392475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988134063U Pending JPH0254242U (ja) | 1988-10-13 | 1988-10-13 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0254242U (ja) |
-
1988
- 1988-10-13 JP JP1988134063U patent/JPH0254242U/ja active Pending