JPH0255739U - - Google Patents
Info
- Publication number
- JPH0255739U JPH0255739U JP13571488U JP13571488U JPH0255739U JP H0255739 U JPH0255739 U JP H0255739U JP 13571488 U JP13571488 U JP 13571488U JP 13571488 U JP13571488 U JP 13571488U JP H0255739 U JPH0255739 U JP H0255739U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- channel type
- buffer circuit
- input buffer
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
第１図は本考案の第１の実施例の入力バツフア
回路図、第２図は第１図の定電流回路としてＰチ
ヤネル型トランジスタを用いた第２の実施例の入
力バツフア回路図、第３図は第１図の定電流回路
としてＮチヤネル型トランジスタを用いた第３の
実施例の入力バツフア回路図、第４図は従来の入
力バツフア回路としてのインバータ回路である。
１……Ｐチヤネル型トランジスタ、２……Ｎチ
ヤネル型トランジスタ、３……定電流回路、４…
…入力端子、５……出力端子、６……Ｐチヤネル
型トランジスタ、７……定電圧回路、８……Ｎチ
ヤネル型トランジスタ。
FIG. 1 is an input buffer circuit diagram of a first embodiment of the present invention, FIG. 2 is an input buffer circuit diagram of a second embodiment using a P-channel transistor as the constant current circuit of FIG. 1, and FIG. The figure shows an input buffer circuit diagram of a third embodiment using N-channel transistors as the constant current circuit of FIG. 1, and FIG. 4 shows an inverter circuit as a conventional input buffer circuit. 1...P channel type transistor, 2...N channel type transistor, 3...constant current circuit, 4...
...input terminal, 5...output terminal, 6...P channel type transistor, 7...constant voltage circuit, 8...N channel type transistor.
Claims (1)
ル型トランジスタのゲート同志を接続して入力端
子とし、ドレイン同志を定電流素子を介して接続
して前記ドレインの一方を出力端子としたことを
特徴とする入力バツフア回路。 (2) 前記定電流素子をゲートソース間電圧を一
定に保つたＰチヤネル型（またはＮチヤネル型）
トランジスタとし、前記出力端子をこのＰチヤネ
ル型（またはＮチヤネル型）トランジスタのドレ
イン端とした請求項１記載の入力バツフア回路。[Claims for Utility Model Registration] (1) The gates of a P-channel transistor and an N-channel transistor are connected together to form an input terminal, and their drains are connected through a constant current element, and one of the drains is an output terminal. An input buffer circuit characterized by: (2) P-channel type (or N-channel type) in which the constant current element maintains a constant gate-source voltage
2. The input buffer circuit according to claim 1, wherein the input buffer circuit is a transistor, and the output terminal is a drain terminal of the P-channel type (or N-channel type) transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13571488U JPH0255739U (en) | 1988-10-17 | 1988-10-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13571488U JPH0255739U (en) | 1988-10-17 | 1988-10-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0255739U true JPH0255739U (en) | 1990-04-23 |
Family
ID=31395590
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13571488U Pending JPH0255739U (en) | 1988-10-17 | 1988-10-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0255739U (en) |
-
1988
- 1988-10-17 JP JP13571488U patent/JPH0255739U/ja active Pending
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