JPH0255751U

JPH0255751U -

Info

Publication number: JPH0255751U
Application number: JP13558888U
Authority: JP
Priority date: 1988-10-18
Filing date: 1988-10-18
Publication date: 1990-04-23
Anticipated expiration: 2003-10-18
Also published as: JPH0713310Y2

Description

[Brief explanation of the drawing]

第１図はこの考案のステレオ表示回路の代表的
な実施例の構成を示す図、第２図は従来のステレ
オ表示回路の構成を示す図である。１はＡＭ復調回路、１ａは混合回路、１ｂは局
部発振回路、１ｃは中間周波増幅回路、１ｄはＡ
Ｍ検波回路、１ｅは自動利得制御回路、１ｆは第
１のローパスフイルタ回路、２はＦＭ復調回路２
で、２ａは高周波増幅回路、２ｂは混合回路、２
ｃは局部発振回路、２ｄは中間周波増幅回路、２
ｅはＦＭ検波回路、３はステレオ復調回路、４は
サブキヤリア信号発生回路、４ａは位相検波回路
、４ｂは第２のローパスフイルタ回路、４ｃは電
圧制御型発振回路、４ｄは第１の分周回路、４ｅ
は第２の分周回路、５はパイロツト信号検波回路
、５ａは同期検波回路、５ｂは第３のローパスフ
イルタ回路、５ｃはトリガ回路、６はステレオイ
ンジケータ、７はステレオスイツチ回路、８は強
制モノラル回路、９はＦＭステレオ―ＡＭ切換回
路である。 FIG. 1 is a diagram showing the configuration of a typical embodiment of the stereo display circuit of this invention, and FIG. 2 is a diagram showing the configuration of a conventional stereo display circuit. 1 is an AM demodulation circuit, 1a is a mixing circuit, 1b is a local oscillation circuit, 1c is an intermediate frequency amplifier circuit, 1d is an A
M detection circuit, 1e is automatic gain control circuit, 1f is first low-pass filter circuit, 2 is FM demodulation circuit 2
2a is a high frequency amplification circuit, 2b is a mixing circuit, 2
c is a local oscillation circuit, 2d is an intermediate frequency amplification circuit, 2
e is an FM detection circuit, 3 is a stereo demodulation circuit, 4 is a subcarrier signal generation circuit, 4a is a phase detection circuit, 4b is a second low-pass filter circuit, 4c is a voltage-controlled oscillation circuit, and 4d is a first frequency dividing circuit. , 4e
is a second frequency dividing circuit, 5 is a pilot signal detection circuit, 5a is a synchronous detection circuit, 5b is a third low-pass filter circuit, 5c is a trigger circuit, 6 is a stereo indicator, 7 is a stereo switch circuit, 8 is a forced monaural The circuit 9 is an FM stereo-AM switching circuit.

Claims

[Scope of utility model registration request]

The AM detection output is passed through the first low-pass filter circuit 1.
an AM demodulation circuit 1 having an automatic gain control circuit 1e that rectifies the FM signal by f and outputs the rectified output voltage as a gain control signal; an FM demodulation circuit 2 that detects an FM signal to obtain a composite signal; A pilot signal included in the voltage-controlled oscillator circuit 4c is detected by a frequency-divided signal obtained by frequency-dividing the output signal of the voltage-controlled oscillation circuit 4c, and this pilot signal is rectified by the third low-pass filter circuit 5b. An FM stereo receiving device comprising a stereo demodulation circuit 3 having a trigger circuit 5c that outputs a stereo indicator signal by
FM-AM stereo in which when the receiving mode is switched to AM mode, the switching output stops the oscillation of the voltage-controlled oscillation circuit 4c, and also controls the trigger circuit 5c to stop outputting the stereo indicator signal. In the receiving device, when the receiving mode is switched from AM mode to FM stereo mode, controlling the trigger circuit 5c,
The voltage output of the first low-pass filter circuit 1f and the voltage output of the third low-pass filter circuit 5b of the automatic gain control circuit 1e, which stop outputting the stereo indicator signal, are connected to a trigger circuit 5c, and A stereo display circuit characterized in that the time constant of the first low-pass filter circuit 1f is larger than the time constant of the third low-pass filter circuit 5b.