JPH0255996B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an interpolation multiplex signal separation circuit, and particularly to
This invention relates to a separation circuit that separates a video signal into a luminance signal and a color signal in the NTSC color television system. For example, in a video signal in the NTSC color television system, a color signal in the form of a carrier signal is interpolated and multiplexed onto the high frequency portion of a combined brightness signal. For this reason, unless the brightness signal and color signal are completely separated using a bandpass filter or the like, they will interfere with each other and degrade the image quality. Normally, if the color signal is simply extracted from the video signal using a bandpass filter centered around the carrier frequency of the color signal, the high frequency components of the luminance signal contained in this signal will become color noise and cause cross color interference. If the carrier color signal remains in the high-frequency component of the luminance signal, dot interference occurs. Recently, research has been conducted to remove these interferences by using a comb filter using an ultrasonic solid state delay line, such as a glass delay line, and the present inventor previously invented a separation circuit shown in FIG. This is a circuit that separates a composite video signal input 1 containing a luminance signal and a color signal into a color signal output C-C and a luminance signal output Y-Y. A composite video input signal is applied to both ends of a series circuit of 3 and a partial voltage load 4 connected thereto, and the delayed output obtained from the output transducer 3' of the ultrasonic solid-state delay line 2 and the partial voltage This is a circuit that combines the signals at both ends of the load to obtain a sum signal and a difference signal between the two, and separates it into a luminance signal and a color signal. The middle point 6 of the net coil 5 is grounded by a capacitor 7 to form an inductive M type circuit, and the voltage applied to the partial voltage load 4 is applied to the anti-resonant coil 9 of the output transducer 3' via the level adjustment circuit 8. It leads to the midpoint of 10. Note that R is a resistor, and C ₁ and C ₀ are capacitors. However, the undelayed signal on the low frequency side passes through the level adjustment circuit 8 to the output transducer 3'.
Since the anti-resinate coil 9 is connected to the midpoint of the anti-resinate coil 9, there is a problem that the anti-resinate coil 9 acts as an inductive reactance with respect to low-frequency signals that are not delayed, resulting in poor phase characteristics. The present invention has been made in order to solve the above-mentioned difficulties, and the difference signal that is separated without changing the phase characteristics of the undelayed signal can generate a separated signal with a stable hue with little phase shift, and output with a flat band. It is an object of the present invention to provide a separation circuit for interpolation multiplexed signals, which can obtain characteristics, is less likely to interfere with each other between an input circuit and an output circuit, and can facilitate level adjustment. In order to achieve this object, the interpolation multiplex signal separation circuit of the present invention converts a composite video input signal containing a luminance signal and a chrominance signal into a delayed signal passed through an ultrasonic solid-state delay line and an ultrasonic solid-state delay line. In an interpolation multiplex signal separation circuit that separates the signal that does not pass through the delay line, combines the delayed signal that has passed and the signal that does not pass, and obtains a sum signal and a difference signal of both, and separates it into a chrominance signal and a luminance signal. , applying a composite video input signal across a series circuit of an ultrasonic solid state delay line input transducer and a partial voltage load connected thereto;
A complementary relationship is given to the delayed signal obtained from the output transducer of the ultrasonic solid-state delay line and the signals at both ends of the partial voltage load, and the non-delayed signals at both ends of the partial voltage load are input to the level adjustment circuit, The non-delayed signal output from the level adjustment circuit is applied to the midpoint of a resistor that is connected to both ends of the anti-registration coil of the output transducer that outputs the delayed signal and is equal to the impedance of the output transducer. The pressure load is composed of a variable resistor, and the level adjustment circuit is composed of an emitter follower circuit. In FIG. 2, parts corresponding to those in FIG. 1 are given the same reference numerals, and detailed explanation thereof will be omitted. It leads to the midpoint 11 of the resistors 10, 10' which are connected and equal to the impedance of the output transducer 3'. Here, a well-known fixed resistor or volume may be used for the level adjustment circuit 8, but as shown in FIG. 13 has the advantage that the input circuit and the output circuit are less likely to interfere with each other, and furthermore, since the output functions as a current source, adjustment by the variable resistor 12 is easy.
In FIG. 3, parts corresponding to those in FIG. 2 are denoted by the same reference numerals, and detailed explanations are omitted. In the above embodiment, the equivalent circuit in the frequency range (approximately 0 to 2.5 MHz) below the operating band of the glass delay line is as shown in FIG. In Figure 4
C ₀ is the constraint capacitance of the input transducer, L is the inductance of each half of the anti-resonant coil, and M is their mutual inductance. In this circuit, if L is approximately equal to M, its input/output impedance is Therefore, the frequency band used by this circuit is 1>
If selected within the range of 4ω ² LC ₀ , this circuit will have no reactance component and no phase shift will occur between the signal voltage applied across the voltage divider load and the input voltage. Moreover, 1
≫In the range of 4ω ² LC ₀ , the input impedance is

The frequency dependence becomes extremely small. It goes without saying that the value of C is determined so that the impedance Z ₀ of the output transducer 3' is equal to the resistors 10 and 10', that is, Z ₀ =R. Next is the frequency range in which the glass delay line operates (approximately
2.5MHz to 4.5MHz), the equivalent circuit is as shown in FIG. Here, R ₀ and C ₂ are the equivalent resonant resistance and equivalent resonant capacitance of the delay line, respectively. In Fig. 5, when the glass delay line starts operating, the above-mentioned equivalent resonant capacitance C ₂ and anti-resonant coil 5 resonate in parallel, and if the Q is made large, it can be seen as an equivalent circuit as shown in Fig. 6. can. At this time, the glass delay line will operate most efficiently if the inductance of the anti-resonate coil is set to 4L and 2R = R ₀ . That is, in the circuit shown in FIG. 6, the signal passing through the glass delay line 2 and the signal applied to the partial voltage load 4 are combined on the output transducer side to form a sum signal or a difference signal, forming a comb filter. . According to the circuit of the embodiment shown in Figs. 2 and 3, the frequency characteristics of the signal that does not pass through the ultrasonic delay line are as shown in Fig. 7, and the frequency characteristics of the signal that has passed through the ultrasonic delay line are as shown in Fig. 8. The final comb-shaped characteristic obtained by adding the two is shown in FIG. 9. In short, since the voltage dividing resistors operate in a complementary manner, it is possible to obtain a flat output characteristic over a band. As explained above, according to the interpolation multiplex signal separation circuit of the present invention, a composite video input signal containing a luminance signal and a chrominance signal is combined with a delayed signal that has passed through an ultrasonic solid-state delay line and an ultrasonic solid-state delay line. In the interpolation multiplex signal separation circuit, the delayed signal that passes and the signal that does not pass are synthesized to obtain a sum signal and a difference signal of both, and the resulting signal is separated into a chrominance signal and a luminance signal. Applying a composite video input signal to both ends of a series circuit of an input transducer of the sonic solid-state delay line and a partial voltage load connected thereto, and a delayed signal obtained from the output transducer of the ultrasonic solid-state delay line; A complementary relationship is given to the signals at both ends of the voltage divider load, and the undelayed signals at both ends of the voltage divider load are input to the level adjustment circuit, and the delayed signal is output to both ends of the antiresist coil of the output transducer. A non-delayed signal output from the level adjustment circuit is applied to the midpoint of the connected resistor that is equal to the impedance of the output transducer, and the voltage division load is configured with a variable resistor, and the level adjustment circuit is configured with an emitter follower circuit. Therefore, the phase characteristics of the undelayed signal do not change, and the separated difference signal has a small phase shift and a stable hue separation signal can be obtained, and the band has an output characteristic that is flat in terms of amplitude. Furthermore, since the voltage dividing load is configured with a variable resistor and the level adjustment circuit is configured with an emitter follower circuit, the input circuit and output circuit are less likely to interfere with each other.Furthermore, since the output functions as a current source, the level adjustment circuit is configured with a variable resistor. Adjustment becomes easier.

[Brief explanation of drawings]

FIG. 1 is a conventional interpolation multiplex signal separation circuit diagram.
FIG. 2 is a circuit diagram showing one embodiment of the present invention, FIG. 3 is a circuit diagram showing a more specific embodiment than FIG. 2, and FIG.
6 to 6 are equivalent circuit diagrams at operating frequencies of the circuit shown in FIG. 2, and FIGS. 7 to 9 are frequency characteristic diagrams of the interpolation multiplex signal separation circuit shown in FIGS. 2 to 3 of the present invention. It is. 1... Synthetic video input signal, 2... Ultrasonic solid state delay line, 3... Input transducer, 3'... Output transducer, 4... Partial pressure load, 5, 9...
...Anti-resonate coil, 6, 10, 11...
Midpoint, 8... Level adjustment circuit, 10, 10'...
Resistance, 12... Volume, 13... Emitsutahorova.

Claims (1)

[Claims] 1 A composite video input signal 1 containing a luminance signal and a chrominance signal is divided into a delayed signal that has passed through the ultrasonic solid-state delay line 2 and a signal that has not passed through the ultrasonic solid-state delay line 2, and the delayed signal that has passed and the signal that has passed are separated. In the interpolation multiplex signal separation circuit, which combines signals that do not correspond to each other to obtain a sum signal and a difference signal, and separates the signal into a color signal C-C and a luminance signal Y-Y, the input of the ultrasonic solid-state delay line 2 is The composite video input signal 1 is applied to both ends of a series circuit of the transducer 3 and the partial voltage load 4 connected thereto, and the delay signal obtained from the output transducer 3' of the ultrasonic solid-state delay line and ,
an output transducer 3' which gives a complementary relationship to the signals at both ends of the voltage divider load, inputs the undelayed signals at both ends of the voltage divider load 4 to the level adjustment circuit 8, and outputs the delayed signal; a resistor 10 connected across the anti-resistance coil 9 and equal to the impedance Z ₀ of the output transducer 3';
The undelayed signal outputted from the level adjustment circuit 8 is applied to the midpoint of 10', and the voltage dividing load 4 is configured by a variable resistor 12, and the level adjustment circuit 8 is configured by an emitter follower circuit 13. An interpolation multiplex signal separation circuit characterized by: