JPH0257038A - Afc control voltage generating circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Summary] I-axis and Q-axis signals that are digitally equalized as input signals in a demodulator are latched by a latch circuit, multiplied by 4 by a quadruple multiplier, and then frequency deviation is determined by a frequency discriminator. Regarding the AFC control voltage generation circuit, which generates a signal and converts it into an analog signal using a D/A converter to generate a control voltage for a local oscillator, the purpose of expanding the frequency pull-in range is to generate 4 from the symbol timing regeneration circuit. double the sample clock,
a clock processing circuit that generates a clock at a point other than the zero-crossing point based on the clock at the zero-crossing point and supplies it to the latch circuit and the frequency discriminator; a four-times sample clock from the symbol timing recovery circuit; a data extraction clock generation circuit that generates a clock for the open portion of the eye pattern and the next clock based on the clock at the zero cross point and the output clock of the clock processing circuit; and another latch circuit that latches the output of the frequency discriminator using a clock from the circuit and sends it to the D/A converter.

In recent years, communications using satellites have become popular. In particular, V S A T (Very Small Aper
With the advent of ture terminal), its utility value is increasing further. Frequency fluctuations pose a problem when communicating using this satellite. The cause of this is
Possible causes include fluctuations in the transponder output frequency due to temperature changes within the satellite, and the Doppler effect.

Therefore, on the receiving side, it is necessary to make the frequency of the local oscillator follow this change, and for this reason AFC (Automatic Frequency Control) is used.
ontrol).

[Industrial application field]

The present invention relates to an AFC control voltage generation circuit, and in particular, a latch circuit latches l-axis and Q-axis signals that are digitally equalized input signals in a demodulator, multiplies the signals by 4 in a quadruple multiplier, and then converts the frequency in a frequency discriminator. This invention relates to an AFC control voltage generation circuit that generates a deviation and converts it into an analog signal using a D/A converter to generate a control voltage for a local oscillator.

[Conventional technology]

FIG. 8 schematically shows a general 4-phase PSK demodulation circuit equipped with an AFC function, in which the input signal is separated into an analog L-axis signal and a Q-axis signal by a 4-phase quadrature detector 11. , this is further converted into a digital signal by the Δ/D converter 12, and then converted into a digital 1-Lance Barsal filter (DTP).
Line equalization is performed at 13 to generate digital equalized outputs for the l-axis and Q-axis, and based on the digital equalized outputs, a carrier wave regeneration circuit (CR) 14 generates identified and reproduced I-axis data and Q-axis data. do.

In this case, if the local oscillation frequency deviates from the input signal frequency by several tens of kilometres, or more,
Carrier wave regeneration circuit 14 i; I does not operate normally.

Therefore, it is necessary to use AFC to change the local oscillation frequency to a frequency that allows the carrier wave regeneration circuit 14 to operate normally. By removing the high frequency component of the output voltage with a loop filter (LPF) 16 and applying a control voltage to a voltage controlled oscillator (VCXO) 17 as a local oscillator of this demodulator,
The local oscillation frequency of the phase detector 11 is controlled, thereby forming an AFC loop shown by a dotted line.

In addition, the operation of each part of this demodulator is controlled by the symbol timing recovery circuit (STR) 18 based on the sonpol timing clock CL K 1 generated based on the output of the filter 13.
In particular, the AFC control voltage generation circuit 15 is supplied with another clock CL K 2, which will be described later, from the symbol timing recovery circuit 18.

FIG. 9 is a block diagram showing this AFC control voltage generation circuit 15, in which the l-axis and Q-axis signals digitally equalized by the filter 13 are latched by a latch circuit (DFF) 1,
The multiplier 2 multiplies the signal by 4, the frequency discriminator 3 discriminates the frequency deviation, and the D/A converter 4 converts it into an analog signal to generate a control voltage for the local oscillator 17.

Furthermore, the frequency discriminator 3 multiplies the l-axis signal or Q-axis signal delayed by one clock and the undelayed Q-axis signal or l-axis signal by delay circuits 31 and 32 for delaying the signal by one clock. is composed of multipliers 33 and 34 for combining, and a subtracter 35 for calculating the difference between the outputs of the multipliers 33 and 34.

The latch operation of the latch circuit 1 and the frequency discriminator 3
The delay operations of the delay circuits 31 and 32 are performed by the clock CLK2 from the symbol timing recovery circuit 18. This clock CL K 2 is generated corresponding to the point in time when the eye pattern of the received signal is widest.

Therefore, as shown in FIG. 10, the received input signal (2) becomes a signal (2) latched by the clock CL K 1, becomes a signal (3) multiplied by four by the quadruple multiplier 2, and becomes a signal (2) multiplied by four by the quadruple multiplier 2. The signal is delayed by a clock time and becomes a signal ■, which is outputted from the subtracter 35 as a frequency discrimination output signal ■ from the D/A converter 4.

Here, the frequency discriminator 3 selects the frequency of the ■axis signal by 5 inches.
(θ+Δωt), the frequency of the Q-axis signal is cos
(θ]Δωt) and is delayed by one clock Δωτ in the delay circuits 31 and 32, the output of the subtracter 35 is 5in(
Δωτ).

Therefore, the amplitude of the output of the frequency discriminator 3 changes according to the frequency deviation, and the frequency is pulled in by the AFC operation.

Here, the reason why the quadruple multiplier 2 is necessary will be explained.

When there is no modulation (when the data is not changing),
Each of the I-axis and Q-axis data input to the frequency discriminator includes only information corresponding to the frequency deviation, and a quadruple multiplier is not required.

During modulation (when data is changing), each of the I-axis and Q-axis data input to the frequency discriminator contains two component information: information to be transmitted and information corresponding to frequency deviation. will be included.

On the other hand, the frequency discriminator requires only information corresponding to the frequency deviation.

Therefore, a quadruple multiplier is used to eliminate the transmitted information.

In a quadruple multiplier, if only the information to be transmitted is included in the data on the ■ axis and the Q axis, the data is divided into four
When modulating, these four points change randomly. By multiplying the angles .theta. and .theta.4 of each data by 4, the data gathers as an "X" mark, the information to be transmitted is deleted, data fluctuation is eliminated, and data obtained by multiplying the actual frequency deviation by 4 is output.

[Problem to be solved by the invention]

If a frequency discriminator is used in such an A F CffdJ control voltage generation circuit, the quadruple multiplier 2 will be required as described above, and the clock will be at the symbol rate. Since Δω is quadrupled, the output of the frequency discriminator 3 becomes 5 inches (4Δωτ).

Here, in order to find the frequency pull-in range when there is no quadruple multiplier 2, we calculate the frequency at which the amplitude output of the frequency discriminator 3 reaches its peak. From 5in (Δωτ)■, Δω−π
/2τ→Δf=1/4τ. On the other hand, when the quadruple multiplier 2 is used, Δω-π/8τ→Δf = 1/16τ from 5in(4Δωτ)−1.

In other words, since the peak frequency becomes 1/4, if the symbol rate of the received signal is 133ksps (symbol 7 seconds), considering the delay of l clocks, 1/τ
-133kHz, and when there is no quadruple multiplier, Δf
= 32kHz and when there is a quadruple multiplier, Δf>8
It becomes kllz.

For this reason, when a quadrupler is used, the frequency range that can be pulled in by AFC is reduced to 1/4 compared to when it is not used, and as long as symbol clock CLK2 is used, it is currently impossible to expand the range of frequencies. The problem was that it was not possible. This effect becomes particularly noticeable as the transmission rate decreases.

Therefore, the present invention latches the digitally equalized ■-axis and Q-axis signals of the input signal in the demodulator with a latch circuit, multiplies them by 4 with a quadruple multiplier, and further generates a frequency deviation with a frequency discriminator. The purpose of this invention is to expand the frequency pull-in range in an AFC control voltage generation circuit that generates a control voltage for a local oscillator by converting it into an analog signal using an A/A converter.

[Means to solve the problem]

In order to solve the above problems, AFCal+ according to the present invention
In the control voltage generation circuit, by changing the processing method of the clock used in the frequency discriminator, the reduction in the frequency pull-in range due to the influence of the quadruple multiplier is attempted to be alleviated.

Therefore, in the present invention, as shown in FIG. 1, based on the four times the sample clock from the symbol timing recovery circuit 18 and the clock at the zero cross point, a clock processing circuit 5 which generates and supplies it to the latch circuit 1 and the frequency discriminator 3, a quadrupled sample count from the symbol timing recovery circuit 18, a clock at the zero crossing point, and a clock processing circuit 5 which generates the clock signal and supplies it to the latch circuit 1 and the frequency discriminator 3; A data extraction clock generation circuit 6 generates a clock for the open part of the eye pattern and the next clock based on the output clock, and an output of the frequency discriminator 3 based on the clock from the data extraction clock generation circuit 6. and another latch circuit 7 that latches and sends the data to the D/A converter 4.

[For production]

Hereinafter, the operation of the present invention will be explained using time charts 1 and 1 in FIG.
Explain using.

First, the clock processing circuit 5 inputs the quadruple sample clock (CLKI) from the symbol timing recovery circuit 18 and the clock at the zero cross point, and uses these clocks to detect the zero cross point of the quadruple sample clock. A clock excluding the dot, that is, a clock at the open part of the eye pattern and clocks on both sides thereof (clock ■ in FIG. 2) is generated and applied to the latch circuit 1 and the frequency discriminator 3.

Then, the latch circuit 1 sends the equalized digital data ■ latched by the respective clocks ■ to the quadrupler 2, and the quadrupler 4f4 divider 2 frequency-discriminates the data ■ obtained by multiplying the data ■ by four. Send to vessel 3.

The 4-multiplied data ■ is delayed by one clock of each of those clocks ■ in the frequency discriminator 3,
After being converted into data ■ and ■, it is output as frequency deviation data ■ and sent to the latch circuit 7.

On the other hand, in the data extraction clock generation circuit, the clock of the open part of the eye pattern is clocked based on the four times the sample clock from the first day of the symbol timing regeneration circuit, the clock of the zero cross point, and the output clock of the clock processing circuit 5. and the next clock (clock ■ in FIG. 2) is generated.

The clock from this data extraction clock generation circuit 6■
Accordingly, the latch circuit 7 sends the data ■ obtained by latching the output ■ of the frequency discriminator 3 to the D/A converter 4.
The control voltage for the local oscillator is generated from .

In this way, the delay clock used in the frequency discriminator 2 or the clock at the zero cross point, which has no meaning as data, is simply removed from the quadruple sample clock, and the frequency is higher than the symbol clock, so the frequency discriminator 2 Since τ due to the delay circuit in 2 can be made small, that is, 1/τ can be made large, the influence of the quadruple multiplier can be reduced.

In the data extraction clock generation circuit 6, since the frequency discriminator 3 processes data that is delayed by one clock, the data extraction circuit 6 processes data other than the data that is being processed with the previous data, that is, the eye pattern. Data other than the clock in the open part and the next clock have no meaning (taking into consideration that the clock ■ is generated and the necessary data is extracted.

〔Example〕

FIG. 3 shows an embodiment of the clock processing circuit 5 used in the AFC control voltage generation circuit according to the present invention. NAN with
D gate 41 and a latch circuit (r) that latches the output of this NAND gate 41 with four times the sample clock X4.
-FF) 42.

FIG. 4 shows an embodiment of a data extraction clock generation circuit. In this embodiment, a shift register 43 delays the zero-cross clock from the symbol timing recovery circuit 18 by one clock by four times the sample clock X4. , a NAND gate 44 between the output of this shift register 43 and the output (see FIG. 2) of the latch circuit 42 in FIG. (See Figure 2)
It is composed of a latch circuit 45 that generates a signal.

Next, the operation of these circuits will be explained with reference to the time chart of FIG.

In the clock processing circuit shown in FIG. 3, the NAND gate 41 outputs a clock other than the zero-cross clock, and the latch circuit 42 synchronizes the timing with the four times the sample clock X4 and supplies it to the latch circuit 1 and the frequency discriminator 3.

This increases the frequency and expands the pull-in range by removing meaningless data at changing points and using other meaningful data.

In the data extraction clock generation circuit shown in Fig. 4, the shift register 43 delays the zero cross clock by one clock to generate a clock [phase], and performs a NAND between this clock [phase] and the clock ■ from the clock processing circuit. As a result, a clock other than this clock [phase] is generated, and the latch circuit 45 generates a clock (2) by timing the sample clock X4 times four times. This eliminates meaningless arithmetic processing outputs that are performed in the frequency discriminator and are not related to the previous data.

〔Effect of the invention〕

As described above, according to the AFC1i control voltage generation circuit of the present invention, meaningful data other than eye pattern changing points can be digitally frequency discriminated using the quadruple sample clock from the symbol timing recovery circuit and the clock at the zero cross point. After inputting the data into the device and performing predetermined arithmetic processing, it generates the clock at the point where the eye pattern opens and the next clock, extracts only meaningful data, and generates the control voltage for the local oscillator. Therefore, it can be seen that the frequency pull-in range in the experimental values shown in FIG. 7 is more than four times larger than that of the conventional example shown in FIG. 6. Also, even if the C/N (carrier wave/noise) is 10,
It is recognized that similar operation is obtained with the present invention.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the principle of the AFC control voltage generation circuit according to the present invention, FIG. 2 is a time chart diagram for explaining the operation of the AFC control voltage generation circuit according to the present invention, and FIG. A circuit diagram showing an embodiment of the clock processing circuit used in the present invention, FIG. 4 is a circuit diagram showing an embodiment of the clock generation circuit for data extraction used in the present invention, and FIG. 5 is a circuit diagram showing an embodiment of the clock processing circuit and data extraction circuit used in the present invention. A time chart diagram for explaining the operation of the clock generation circuit. Figure 6 is a graph diagram showing the frequency discrimination characteristics of the conventional example using experimental values. Figure 7 is a graph diagram showing the frequency discrimination characteristics of the present invention using experimental values. Fig. 8 is a block diagram schematically showing a 4-phase PSK demodulator, Fig. 9 is a block diagram showing a conventional AFC control voltage generation circuit, and Fig. 10 is a block diagram showing a conventional AFC control voltage generation circuit. Operation time chart FIG. 11 is a diagram for explaining the operation of the quadruple multiplier. In FIG. 1, 1... Latch circuit, 2... Quadruple multiplier, 3... Frequency discriminator, 4... D/A converter, 5... Clock processing circuit, 6... Clock generation circuit for data extraction, 18... Symbol timing regeneration circuit. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] The digitally equalized I-axis and Q-axis signals of the input signal in the demodulator are latched by the latch circuit (1), and the quadrupler (
In the AFC control voltage generation circuit, which multiplies the voltage by 4 in step 2), generates a frequency deviation in the frequency discriminator (3), converts it to an analog signal in the D/A converter (4), and generates the control voltage for the local oscillator. , based on the quadruple sample clock from the symbol timing recovery circuit (18) and the clock at the zero crossing point,
Out of the quadruple sample clock, clocks other than the zero-crossing point are generated and used in the latch circuit and the frequency discriminator (
3), the four times the sample clock from the symbol timing recovery circuit (18), the clock at the zero crossing point, and the output clock of the clock processing circuit (5), A data extraction clock generation circuit (6) that generates the clock for the open part of the eye pattern and the next clock; and the output of the frequency discriminator (3) using the clock from the data extraction clock generation circuit (6). Latch the D/
An AFC control voltage generation circuit comprising: another latch circuit (7) for sending data to an A converter (4).