JPH0257614U - - Google Patents
Info
- Publication number
- JPH0257614U JPH0257614U JP13689488U JP13689488U JPH0257614U JP H0257614 U JPH0257614 U JP H0257614U JP 13689488 U JP13689488 U JP 13689488U JP 13689488 U JP13689488 U JP 13689488U JP H0257614 U JPH0257614 U JP H0257614U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier circuit
- stage
- output
- stage amplifier
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Amplifiers (AREA)
Description
第１図は、本考案の一実施例を示す回路図、及
び第２図は従来の増幅器を示す回路図である。
１８……前段増幅回路、１９……後段増幅回路
、２８……基準電源、２９……第１バツフア増幅
回路、３０……第２バツフア増幅回路、３１……
ヘツドフオン。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional amplifier. 18... Pre-stage amplifier circuit, 19... Post-stage amplifier circuit, 28... Reference power supply, 29... First buffer amplifier circuit, 30... Second buffer amplifier circuit, 31...
Headhunt.
Claims (1)
回路と、 バイアス用基準電源と、 該基準電源から得られる基準電圧を前記前段及
び後段増幅回路にバイアス電圧として印加する第
１バツフア増幅回路と、 前記基準電圧と等しい値の出力電圧を発生する
第２バツフア増幅回路と から成り、前記後段増幅回路の出力端と前記第
２バツフア増幅回路の出力端との間に負荷を接続
し得る様にしたことを特徴とする増幅器。 (2) 前記第１及び第２バツフア増幅回路は、１
００％負帰還型の増幅回路で構成されることを特
徴とする請求項第１項記載の増幅器。 (3) 前記後段増幅回路は、正及び負入力端子と
、負荷に接続される出力端子と、前記出力端子に
得られる出力信号を負入力端子に負帰還する負帰
還回路とを備え、前記第１バツフア増幅回路の出
力電圧は、前記正及び負入力端子にバイアス電圧
として印加されることを特徴とする請求項第１項
記載の増幅器。 (4) 前記前段増幅回路及び前記後段増幅回路は
、それぞれ正及び負入力端子と出力端子とを有し
、前記第１バツフア増幅回路の出力バイアス電圧
を前記前段増幅回路の正入力端子及び前記後段増
幅回路の負入力端子に印加するとともに、前記前
段増幅回路の出力信号を前記後段増幅回路の正入
力端子に印加する様にしたことを特徴とする請求
項第１項記載の増幅器。[Claims for Utility Model Registration] (1) A front-stage amplifier circuit that amplifies an input signal, a rear-stage amplifier circuit that amplifies an output signal of the front-stage amplifier circuit, a reference power source for bias, and a reference voltage obtained from the reference power source. a first buffer amplifier circuit that applies a bias voltage to the front-stage and rear-stage amplifier circuits; and a second buffer amplifier circuit that generates an output voltage equal to the reference voltage; An amplifier characterized in that a load can be connected between the output terminal of the second buffer amplifier circuit and the output terminal of the second buffer amplifier circuit. (2) The first and second buffer amplifier circuits include 1
2. The amplifier according to claim 1, comprising a 00% negative feedback type amplifier circuit. (3) The latter-stage amplifier circuit includes positive and negative input terminals, an output terminal connected to a load, and a negative feedback circuit that negatively feeds back an output signal obtained at the output terminal to a negative input terminal, and 2. The amplifier according to claim 1, wherein the output voltage of the one-buffer amplifier circuit is applied as a bias voltage to the positive and negative input terminals. (4) The pre-stage amplifier circuit and the post-stage amplifier circuit each have a positive and negative input terminal and an output terminal, and the output bias voltage of the first buffer amplifier circuit is applied to the positive input terminal of the pre-stage amplifier circuit and the post-stage amplifier circuit. 2. The amplifier according to claim 1, wherein the signal is applied to the negative input terminal of the amplifier circuit, and the output signal of the pre-stage amplifier circuit is applied to the positive input terminal of the post-stage amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988136894U JPH0543532Y2 (en) | 1988-10-20 | 1988-10-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988136894U JPH0543532Y2 (en) | 1988-10-20 | 1988-10-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0257614U true JPH0257614U (en) | 1990-04-25 |
| JPH0543532Y2 JPH0543532Y2 (en) | 1993-11-02 |
Family
ID=31397828
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988136894U Expired - Lifetime JPH0543532Y2 (en) | 1988-10-20 | 1988-10-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0543532Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6185924U (en) * | 1984-11-09 | 1986-06-05 |
-
1988
- 1988-10-20 JP JP1988136894U patent/JPH0543532Y2/ja not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6185924U (en) * | 1984-11-09 | 1986-06-05 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0543532Y2 (en) | 1993-11-02 |
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