JPH0260157A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0260157A JPH0260157A JP63211862A JP21186288A JPH0260157A JP H0260157 A JPH0260157 A JP H0260157A JP 63211862 A JP63211862 A JP 63211862A JP 21186288 A JP21186288 A JP 21186288A JP H0260157 A JPH0260157 A JP H0260157A
- Authority
- JP
- Japan
- Prior art keywords
- film
- electrode
- metal oxide
- oxide film
- nitrogen compound
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 35
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 35
- 239000010703 silicon Substances 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 229910017464 nitrogen compound Inorganic materials 0.000 claims abstract description 22
- 150000002830 nitrogen compounds Chemical class 0.000 claims abstract description 22
- 239000003990 capacitor Substances 0.000 claims abstract description 18
- 150000002736 metal compounds Chemical class 0.000 claims description 19
- 229910021332 silicide Inorganic materials 0.000 claims description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 6
- 239000002184 metal Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 25
- 239000000758 substrate Substances 0.000 abstract description 22
- 239000012535 impurity Substances 0.000 abstract description 16
- 230000007704 transition Effects 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 11
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 238000004544 sputter deposition Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract 1
- 230000014759 maintenance of location Effects 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 14
- 229920005591 polysilicon Polymers 0.000 description 13
- 239000000126 substance Substances 0.000 description 7
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910020968 MoSi2 Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910010421 TiNx Inorganic materials 0.000 description 1
- 229910008479 TiSi2 Inorganic materials 0.000 description 1
- 229910008814 WSi2 Inorganic materials 0.000 description 1
- 239000013543 active substance Substances 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- DFJQEGUNXWZVAH-UHFFFAOYSA-N bis($l^{2}-silanylidene)titanium Chemical compound [Si]=[Ti]=[Si] DFJQEGUNXWZVAH-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に容量部の構造が下地電
極として、シリコン基板もしくはポリシリコン電極やシ
リサイド電極を用い、誘電体材料として金属酸化膜を用
いて構成されている半導体装置に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device, and in particular, the present invention relates to a semiconductor device, and in particular, the structure of a capacitor part uses a silicon substrate, a polysilicon electrode, or a silicide electrode as a base electrode, and a metal oxide film as a dielectric material. The present invention relates to a semiconductor device configured using.
DRAM(ダイナミック・ランダム・アクセス・メモリ
)の如く、構成要素として容量を備えた半導体装置に於
いては、容量部の面積を極力小さくすることが上記半導
体装置の高密度化を進める上で重要である。In a semiconductor device such as a DRAM (dynamic random access memory) that has a capacitor as a component, it is important to reduce the area of the capacitor part as much as possible in order to increase the density of the semiconductor device. be.
容量部の占める面積を小さくするためには、従来の5i
f2やS i3N4よりも大きな誘電率を持つ誘電体材
料を用いるのが有利であり、このためTa酸化物、Ti
酸化物、Zr酸化物、Hf酸化物などからなる金属酸化
膜、さらにはBaTi0゜の如き強誘電体材料からなる
膜を用いることが試みられている。これら誘電体膜を形
成する方法としては、■Ta、Ti、Zr、Hfなどの
金属材料をターゲットとしてスパッタ蒸着法により基板
表面に金属膜を形成した後にこれを酸化する方法、■ス
パッタ蒸着を酸素雰囲気中で行い基板上に金属酸化物と
して堆積する手法、あるいは■CVD法により基板上に
金属酸化膜を堆積する方法などが用いられる。In order to reduce the area occupied by the capacitor, the conventional 5i
It is advantageous to use a dielectric material with a larger permittivity than f2 or Si3N4, and for this reason Ta oxide, Ti
Attempts have been made to use metal oxide films made of oxides, Zr oxides, Hf oxides, etc., and films made of ferroelectric materials such as BaTi0°. Methods for forming these dielectric films include: (1) forming a metal film on the substrate surface by sputter deposition using a metal material such as Ta, Ti, Zr, or Hf as a target, and then oxidizing it; (2) using sputter deposition with oxygen; A method of depositing a metal oxide film on a substrate in an atmosphere, or a method of depositing a metal oxide film on a substrate by CVD method, etc. are used.
Ta酸化物、Ti酸化物などの絶縁性を有する金属酸化
物からなる膜を単結晶シリコン上あるいは多結晶シリコ
ン(ポリシリコン)電極上に形成すると、本来得られる
べき高い容量値が低下してしまうという欠点がある。こ
の現象は特に金属酸化膜の膜厚が薄いほど顕著となる。When a film made of an insulating metal oxide such as Ta oxide or Ti oxide is formed on single crystal silicon or polycrystalline silicon (polysilicon) electrodes, the high capacitance value that should originally be obtained decreases. There is a drawback. This phenomenon becomes particularly noticeable as the metal oxide film becomes thinner.
この原因は金FiJ化膜とシリコン又はポリシリコン電
極との間にSiOxの如き誘電率の低い遷移層(比誘電
率4程度)が形成されることによる。即ち、観察される
容量値は金属酸化膜の容量と遷移層の容量との直列接続
された値になり、金属酸化膜の膜厚が薄く当該膜の容量
が大きい場合には、観察される容量値は 容量の小さな
遷移層の容量に大きく支配されるからである。This is caused by the formation of a low dielectric constant transition layer (relative dielectric constant about 4) such as SiOx between the gold FiJ film and the silicon or polysilicon electrode. In other words, the observed capacitance value is the value that is the series connection of the capacitance of the metal oxide film and the capacitance of the transition layer.If the thickness of the metal oxide film is thin and the capacitance of the film is large, the observed capacitance value This is because the value is largely dominated by the capacitance of the transition layer, which has a small capacitance.
シリコンと金属酸化膜との界面に遷移層が形成される理
由は、金属酸化膜が酸素を放出し易い(還元され易い)
性質を持ち、シリコンの如き酸化され易い活性な物質に
接すると酸素を放出する結果、界面にSiOx層が形成
されるものである。The reason why a transition layer is formed at the interface between silicon and metal oxide film is that metal oxide film easily releases oxygen (easily reduced).
When it comes into contact with an active substance that is easily oxidized, such as silicon, it releases oxygen, and as a result, a SiOx layer is formed at the interface.
この遷移層の膜厚は、透過型電子顕微鏡による高解像度
の断面観察によれば、20〜35人と極めて薄い。しか
し、例えば比誘電率25.膜厚100人の金属酸化膜を
形成した場合には、観察される容量値は遷移層の無い場
合に比べ45%以下になってしまう。従って、シリコン
上に金属酸化膜を形成した場合には、金属酸化膜が本来
布する誘電率の高い膜としての性質を生かすことは出来
ない。According to high-resolution cross-sectional observation using a transmission electron microscope, the thickness of this transition layer is extremely thin by 20 to 35 people. However, for example, the dielectric constant is 25. If a metal oxide film with a thickness of 100% is formed, the observed capacitance value will be 45% or less compared to the case without a transition layer. Therefore, when a metal oxide film is formed on silicon, the property of the metal oxide film as a film with a high dielectric constant cannot be utilized.
上記した遷移層の問題を改善する1つの手段として、酸
化され易いシリコンの代わりに活性度のより低い電極拐
料膜の上に絶縁性を有する金属酸化膜を設けることが行
われている。即ち、シリコン基板上にいったんWSi2
.MoSi2.TiSi2の如き金属シリサイド膜を設
けたのちに絶縁性を有する金属酸化膜を形成するもので
ある。しかし、金属シリサイドは組成としてシリコンが
含まれるため、金属酸化膜との反応を防止するためには
膜形成後のプロセスを350℃以下の温度におさえる必
要がある。このような限定された条件では、半導体装置
を作る上で制約が大きく、応用が限定されてしまう欠点
を持っていた。As one means for improving the above-mentioned problem of the transition layer, a metal oxide film having insulating properties is provided on an electrode thinning film having a lower activity instead of silicon, which is easily oxidized. That is, once WSi2 is placed on the silicon substrate,
.. MoSi2. After a metal silicide film such as TiSi2 is provided, an insulating metal oxide film is formed. However, since metal silicide contains silicon as a composition, it is necessary to keep the temperature of the process after film formation below 350° C. in order to prevent reaction with the metal oxide film. Such limited conditions have the drawback of severely restricting the fabrication of semiconductor devices and limiting their applications.
本発明の半導体装置は、シリコン基板上にもしくはポリ
シリコン電極や金属シリサイド電極上に、導電性を有す
る窒素化合物もしくは金属化合物からなる膜を設け、続
いて誘電体どしての絶縁性を有する金属酸化膜を設け、
次に電極を設けて構成される容量を有している。In the semiconductor device of the present invention, a film made of a conductive nitrogen compound or a metal compound is provided on a silicon substrate or a polysilicon electrode or a metal silicide electrode, and then a film made of an electrically conductive nitrogen compound or a metal compound is formed as a dielectric. Provide an oxide film,
Next, it has a capacitor configured by providing an electrode.
絶縁性を有する金属酸化膜は導電性を有する窒素化合物
もしくは金属化合物からなる膜と接しシリコンとの接触
がないため、SiOxの如き遷移層は形成されない。従
って絶縁性を有する金属酸化膜が本来布する大きな容量
窒素を実現することができる。Since the insulating metal oxide film is in contact with a conductive film made of a nitrogen compound or a metal compound and has no contact with silicon, a transition layer such as SiOx is not formed. Therefore, it is possible to realize a large nitrogen capacitance that is originally provided by an insulating metal oxide film.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1図は本発明の第1の実施例の容量の断面構造を説明
する図である。図において、1はシリコン基板、2は絶
縁膜、3はシリコン基板1の表面に設けられた該基板と
逆型の高濃度不純物領域、4は導電性を有する窒素化合
物もしくは金属化合物の膜、5は絶縁性を有する金属酸
化膜、6は電極をそれぞれ示す。当該容量は、導電性を
有する窒素化合物もしくは金属化合物の膜4を下地電極
とし、絶縁性を有する金属酸化膜5を誘電体に用い、電
極6を上部電極として容量が構成される。FIG. 1 is a diagram illustrating a cross-sectional structure of a capacitor according to a first embodiment of the present invention. In the figure, 1 is a silicon substrate, 2 is an insulating film, 3 is a high concentration impurity region provided on the surface of the silicon substrate 1 and is of the opposite type to the substrate, 4 is a film of a nitrogen compound or metal compound having conductivity, and 5 6 indicates an insulating metal oxide film, and 6 indicates an electrode. The capacitor is constructed using a conductive nitrogen compound or metal compound film 4 as a base electrode, an insulating metal oxide film 5 as a dielectric, and an electrode 6 as an upper electrode.
本実施例では、導電性を有する窒素化合物もしくは金属
化合物の膜4はシリコン基板1の表面に設けられた高濃
度不純物領域3に接続されており、従って不純物領域3
と前記電極6との間に電圧を加えることにより当該容量
は機能する。In this embodiment, the conductive nitrogen compound or metal compound film 4 is connected to the high concentration impurity region 3 provided on the surface of the silicon substrate 1.
The capacitor functions by applying a voltage between the electrode 6 and the electrode 6.
当該容量の形成方法としては、シリコン基板1の表面に
周知の技術を用いて選択的に前記膜2を設け、次に熱拡
散もしくはイオン打ち込みの技術を用いて高濃度不純物
領域3を形成する。次に、TiNx、WNxなどの導電
性を有する窒素化合物膜もしくはTiW、AuSn、A
u5nAj7などの金属化合物膜4を、スパッタ蒸着法
あるいは化学気相成長法などの手法を用いて形成する。The method for forming the capacitor is to selectively provide the film 2 on the surface of the silicon substrate 1 using a well-known technique, and then form the high concentration impurity region 3 using a thermal diffusion or ion implantation technique. Next, a nitrogen compound film having conductivity such as TiNx, WNx or TiW, AuSn, A
A metal compound film 4 such as u5nAj7 is formed using a method such as sputter deposition or chemical vapor deposition.
当該導電性を有する金属酸化膜の好ましい膜厚は200
〜1000人である。次に、周知の技術を用いて当該膜
4を選択的にエツチングし所望の領域に膜を残す。次に
、T a gos、 Z r 02#Hf 02あるい
はB a T i O3の如き絶縁性を有する金属酸化
膜5を、スパッタ蒸着法あるいは化学気相成長法などの
手法を用いて形成する。次に、電極6を所望の領域に形
成し、本実施例になる容量が形成される。なお、上記し
た構造の容量において、高濃度不純物領域3の導電型は
シリコン基板1と逆型であっても、あるいは同型であっ
ても良く、その選択は自由である。さらに、当該高濃度
不純物領域3を設けずに、直接シリコン基板1に接触せ
しめても良い。The preferred thickness of the conductive metal oxide film is 200 mm.
~1000 people. Next, the film 4 is selectively etched using well-known techniques to leave the film in desired areas. Next, an insulating metal oxide film 5 such as T a gos, Z r 02 #Hf 02 or B a T i O3 is formed using a method such as sputter deposition or chemical vapor deposition. Next, the electrode 6 is formed in a desired region, and the capacitor of this embodiment is formed. In the capacitance of the above-described structure, the conductivity type of the high concentration impurity region 3 may be the opposite type to the silicon substrate 1 or the same type, and the selection thereof is free. Furthermore, the high concentration impurity region 3 may not be provided and may be brought into direct contact with the silicon substrate 1.
なお、第1図に示す容器部の構造では、導電性を有する
窒素化合物もしくは金属化合物の膜4が高濃度不純物領
域30表面および絶縁膜2の表面の一部に設けられたが
、本発明の目的であるシリコン基板との間に・遷移層を
形成しないという点で第2図に示すように高濃度不純物
領域30表面にのみ導電性を有する窒素化合物もしくは
金属化合物の膜4を設けても良いことは言うまでもない
。In the structure of the container shown in FIG. 1, the conductive nitrogen compound or metal compound film 4 is provided on the surface of the high concentration impurity region 30 and a part of the surface of the insulating film 2. In order to avoid forming a transition layer between the target silicon substrate and the silicon substrate, a conductive nitrogen compound or metal compound film 4 may be provided only on the surface of the high concentration impurity region 30, as shown in FIG. Needless to say.
第3図は、本発明の第2の実施例の容量の断面構造を説
明する図である。図において、第1図と同記号は同一物
質もしくは同一の機能を有する物質であり、7はポリシ
リコン電極を示す。FIG. 3 is a diagram illustrating a cross-sectional structure of a capacitor according to a second embodiment of the present invention. In the figure, the same symbols as in FIG. 1 indicate the same materials or substances having the same function, and 7 indicates a polysilicon electrode.
当該構造の容量は、ポリシリコン電極7の表面に設けら
れた導電性を有する窒素化合物もしくは金属化合物の膜
4と、絶縁性を有する金属酸化膜5と、電極6とから容
量が構成される。導電性を有する金属酸化膜4はポリシ
リコン電極7に接触しているため、ポリシリコン電極に
加えられた電圧が導電性を有する金属酸化膜4にそのま
ま加わる。The capacitance of this structure is composed of a conductive nitrogen compound or metal compound film 4 provided on the surface of the polysilicon electrode 7, an insulating metal oxide film 5, and an electrode 6. Since the conductive metal oxide film 4 is in contact with the polysilicon electrode 7, the voltage applied to the polysilicon electrode is directly applied to the conductive metal oxide film 4.
第4図は、本発明の第3の実施例を説明するための断面
図であり、容量をDRAM (ダイナミック・ランダム
・アクセス・メモリー)に適用した場合の断面構造を示
す。図において、第1図と同記号は同一物質もしくは同
一機能を有する物質であり、21および22は絶縁膜、
31および32は高濃度不純物領域、61は電極、62
はビット電極、72はワード電極をそれぞれ示す。FIG. 4 is a cross-sectional view for explaining the third embodiment of the present invention, and shows a cross-sectional structure when the capacitor is applied to a DRAM (dynamic random access memory). In the figure, the same symbols as in FIG. 1 are the same substances or substances having the same function, 21 and 22 are insulating films,
31 and 32 are high concentration impurity regions, 61 is an electrode, 62
72 represents a bit electrode, and 72 represents a word electrode.
当該構造の容量は、導電性を有する窒素化合物もしくは
金属化合物の膜4と、絶縁性を有する金属酸化膜5と電
極61とで構成される。導電性を有する窒素化合物もし
くは金属化合物の膜4は高濃度不純物領域32に接して
おり、当該高濃度不純物領域32に加えられた電圧が導
電性を有する金属酸化膜4に加わる。The capacitor of this structure is composed of a conductive nitrogen compound or metal compound film 4, an insulating metal oxide film 5, and an electrode 61. The conductive nitrogen compound or metal compound film 4 is in contact with the high concentration impurity region 32, and the voltage applied to the high concentration impurity region 32 is applied to the conductive metal oxide film 4.
第5図は本発明の第4の実施例を示す断面図であり、容
量を他の構造のDRAMに適用した場合の断面構造を示
す。図において、第3図および第4図と同記号は、同一
物質もしくは同一機能を有する物質である。FIG. 5 is a cross-sectional view showing a fourth embodiment of the present invention, and shows a cross-sectional structure when the capacitor is applied to a DRAM of another structure. In the figures, the same symbols as in FIGS. 3 and 4 indicate the same substances or substances having the same functions.
当該構造容量では、導電性を有する窒素化合物もしくは
金属化合物の膜4はポリシリコン電極7に、また当該ポ
リシリコン電極7は高濃度不純物領域32に接している
ため、高濃度不純物領域32に加えられた電圧はポリシ
リコン電極7および導電性を有する窒素化合物もしくは
金属化合物の膜4にそのまま印加される。In this structural capacitance, the conductive nitrogen compound or metal compound film 4 is in contact with the polysilicon electrode 7, and the polysilicon electrode 7 is in contact with the high concentration impurity region 32, so that it is not added to the high concentration impurity region 32. The voltage is directly applied to the polysilicon electrode 7 and the conductive nitrogen compound or metal compound film 4.
第6図は本発明の第5の実施例を示す断面図であり、他
の構造のDRAMに適用した場合の断面構造を示す。図
において、第1図および第4図と同記号は同一物質もし
くは同一機能を有する物質であり、33はシリコン基板
1と同型の高濃度不純物領域、75は埋込電極である。FIG. 6 is a cross-sectional view showing a fifth embodiment of the present invention, and shows a cross-sectional structure when applied to a DRAM of another structure. In the figure, the same symbols as in FIGS. 1 and 4 are the same substances or substances having the same function, 33 is a high concentration impurity region of the same type as the silicon substrate 1, and 75 is a buried electrode.
当該構造容量は、シリコン基板lの表面に溝を形成し、
当該溝の側壁および底部壁に容量を形成するものである
。溝内壁部の構造は、高濃度不純物領域33が形成され
たシリコン基板の表面に導電性を有する窒素化合物もし
くは金属化合物の膜4が設けられ、次に絶縁性を有する
金属酸化膜5が設けられ、次に溝内をうめこむ埋込電極
75が設けられ、容量を構成している。The structural capacitance forms a groove on the surface of the silicon substrate l,
A capacitance is formed on the side and bottom walls of the groove. The structure of the inner wall of the groove is such that a conductive nitrogen compound or metal compound film 4 is provided on the surface of a silicon substrate on which a high concentration impurity region 33 is formed, and then an insulating metal oxide film 5 is provided. Next, a buried electrode 75 is provided to fill the inside of the groove, forming a capacitor.
以上説明したように本発明は、酸素に対して活性なシリ
コン基板やポリシリコン電極やシリサイド電極の表面に
いったん導電性を有する窒素化合物もしくは金属化合物
の膜を設けた後に絶縁性を有する金属酸化膜を設けるた
め、SiOxの如き遷移層の形成による容量の低下が防
止できる効果がある。また、本発明になる容量は、誘電
体としての金属酸化膜および導電性を有する窒素化合物
もしくは金属化合物とも耐熱性にも優れており。As explained above, in the present invention, a film of a nitrogen compound or a metal compound having conductivity is once provided on the surface of a silicon substrate, a polysilicon electrode, or a silicide electrode that is active against oxygen, and then a metal oxide film having an insulating property is formed. This has the effect of preventing a decrease in capacity due to the formation of a transition layer such as SiOx. Further, the capacitor of the present invention has excellent heat resistance with both a metal oxide film as a dielectric and a conductive nitrogen compound or metal compound.
600℃でも電気特性に変化は見られなかった。No change in electrical properties was observed even at 600°C.
第1図および第2図は本発明の第1の実施例を説明する
ための断面図、第3図は本発明の第2の実施例を説明す
るための断面図、第4図は本発明の第3の実施例を説明
するための断面図、第5図は本発明の第4の実施例を説
明するたやの断面図、第6図は本発明の第5の実施例を
説明するための断面図である。
1・・・・・・シリコン基板、2・・・・・・絶縁膜、
3・・・・・・高濃度不純物領域、4・・・・・・導電
性を有する窒素化合物もしくは金属化合物膜、5・・・
・・・絶縁性を有する金属酸化膜、6・・・・・・電極
、7・・・・・・ポリシリコン電極、75・・・・・・
埋込電極。
代理人 弁理士 内 原 音
生
図
手
図1 and 2 are cross-sectional views for explaining the first embodiment of the present invention, FIG. 3 is a cross-sectional view for explaining the second embodiment of the present invention, and FIG. 4 is a cross-sectional view for explaining the second embodiment of the present invention. FIG. 5 is a cross-sectional view of the shaft for explaining the fourth embodiment of the present invention, and FIG. 6 is a cross-sectional view for explaining the fifth embodiment of the present invention. FIG. 1... Silicon substrate, 2... Insulating film,
3...High concentration impurity region, 4...Nitrogen compound or metal compound film having conductivity, 5...
...Insulating metal oxide film, 6...Electrode, 7...Polysilicon electrode, 75...
Implanted electrode. Agent Patent Attorney Uchihara Onsei Zu Tezu
Claims (1)
素化合物もしくは金属化合物からなる膜と、絶縁性を有
する金属酸化膜と、電極とを順次積層して構成した容量
を含むことを特徴とする半導体装置。A semiconductor device comprising a capacitor formed by sequentially stacking a conductive film made of a nitrogen compound or a metal compound, an insulating metal oxide film, and an electrode on a silicon or metal silicide layer. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63211862A JPH0736438B2 (en) | 1988-08-25 | 1988-08-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63211862A JPH0736438B2 (en) | 1988-08-25 | 1988-08-25 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0260157A true JPH0260157A (en) | 1990-02-28 |
| JPH0736438B2 JPH0736438B2 (en) | 1995-04-19 |
Family
ID=16612839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63211862A Expired - Lifetime JPH0736438B2 (en) | 1988-08-25 | 1988-08-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0736438B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5192871A (en) * | 1991-10-15 | 1993-03-09 | Motorola, Inc. | Voltage variable capacitor having amorphous dielectric film |
| JPH0682599A (en) * | 1992-02-13 | 1994-03-22 | Elf Atochem Sa | Method for sealing liquid/solid material in various concentrations into (meta) acrylic resin |
| WO2002037567A1 (en) * | 2000-11-01 | 2002-05-10 | Sony Corporation | Capacitor element and production method therefor |
| US7335570B1 (en) | 1990-07-24 | 2008-02-26 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming insulating films, capacitances, and semiconductor devices |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6072261A (en) * | 1983-09-28 | 1985-04-24 | Fujitsu Ltd | Semiconductor memory |
| JPS6074556A (en) * | 1983-09-30 | 1985-04-26 | Fujitsu Ltd | Capacitor |
| JPS60107854A (en) * | 1983-11-16 | 1985-06-13 | Hitachi Ltd | capacitor |
| JPH0194645A (en) * | 1987-10-06 | 1989-04-13 | Toshiba Corp | Manufacture of semiconductor device |
-
1988
- 1988-08-25 JP JP63211862A patent/JPH0736438B2/en not_active Expired - Lifetime
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6072261A (en) * | 1983-09-28 | 1985-04-24 | Fujitsu Ltd | Semiconductor memory |
| JPS6074556A (en) * | 1983-09-30 | 1985-04-26 | Fujitsu Ltd | Capacitor |
| JPS60107854A (en) * | 1983-11-16 | 1985-06-13 | Hitachi Ltd | capacitor |
| JPH0194645A (en) * | 1987-10-06 | 1989-04-13 | Toshiba Corp | Manufacture of semiconductor device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7335570B1 (en) | 1990-07-24 | 2008-02-26 | Semiconductor Energy Laboratory Co., Ltd. | Method of forming insulating films, capacitances, and semiconductor devices |
| US5192871A (en) * | 1991-10-15 | 1993-03-09 | Motorola, Inc. | Voltage variable capacitor having amorphous dielectric film |
| WO1993008610A1 (en) * | 1991-10-15 | 1993-04-29 | Motorola, Inc. | Voltage variable capacitor having amorphous dielectric film |
| JPH0682599A (en) * | 1992-02-13 | 1994-03-22 | Elf Atochem Sa | Method for sealing liquid/solid material in various concentrations into (meta) acrylic resin |
| WO2002037567A1 (en) * | 2000-11-01 | 2002-05-10 | Sony Corporation | Capacitor element and production method therefor |
| US7157738B2 (en) | 2000-11-01 | 2007-01-02 | Sony Corporation | Capacitor element and its manufacturing method |
| EP1331668A4 (en) * | 2000-11-01 | 2007-03-21 | Sony Corp | CAPACITOR ELEMENT AND METHOD FOR PRODUCING THE SAME |
| KR100830356B1 (en) * | 2000-11-01 | 2008-05-20 | 소니 가부시끼 가이샤 | Capacitor element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0736438B2 (en) | 1995-04-19 |
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