JPH0260444U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of the present invention, FIG. 2 is a circuit diagram of a conventional example, and FIG. 3 is a circuit diagram of an embodiment of the circuit diagram of the present invention. 1 is a secondary battery, 2 is a switch, 4 is a capacitor, 6 is a constant voltage rectifier, 7 is an FET, 19 is a rectifier, 21
is V・REG, 25 is a transistor, 34 is a transformer, 37 is V・DET, 40 is a DC motor, 43
is a voltage detection circuit, 44 is a constant voltage circuit, 45 is an OS
It is C.

Claims (1)

[Scope of utility model registration request] P-channel type and N-channel type of field effect transistor (hereinafter referred to as "FET"), respective gate and source voltage resistors, impedance lowering capacitors, voltage detection constant voltage rectifiers, and their current limiting resistors. voltage detection circuit,
At the final stage, there is a constant voltage circuit consisting of an integrated circuit voltage regulator (hereinafter referred to as "V REG") connected by a rectifier in series with a resistor, and a capacitor for reducing impedance at its input and output terminals, and at its output terminal. An unstable multivibrator circuit (hereinafter referred to as "OSC") to which voltage is applied via a connected rectifier, a step-up transformer connected to its output terminal with a capacitor, and a transistor whose generated voltage is OSC. a rectifier that prevents reverse current from flowing to the output voltage, a rectifier that rectifies the output voltage of the step-up transformer, an integrated circuit voltage detector (hereinafter referred to as "V DET") that detects the voltage, and a constant voltage that limits the input voltage. Rectifier and V
- An overdischarge prevention circuit characterized by comprising a load current intermittent FET connected to the output terminal of the DET with a resistor, and a capacitor for reducing the impedance between the gate and source of the FET.