JPH0262043A - Pattern for size measurement - Google Patents

Abstract

PURPOSE:To indirectly measure a width of a pattern which has been etched by a method wherein two or more line patterns are arranged and etched simultaneously and resistance values are compared electrically in a posterior process or a final process. CONSTITUTION:For example, in a gate polysilicon formation process of a semiconductor device manufacturing process, a line 1 whose size is identical to 1mum of a design minimum width of gate polysilicon and a line 2 of 2mum of double the design width are formed to be an identical length of 40mum. External extraction electrode pads 3a, 3b, 4a, 4b are arranged at both ends of individual line patterns. In a next process or a final process, electric resistances between the pads 3a and 3b of the line 1 and between the pads 4a and 4b of the line 2 are measured. Thereby; a width of the patterns which have been etched can be measured indirectly.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a pattern for measuring etching dimensions.

[Conventional technology]

Conventionally, there was no pattern for measuring dimensions of this type, and the required pattern was directly measured using an optical dimension measuring machine after etching.

[Problem to be solved by the invention]

The above-mentioned conventional dimension measurement has the disadvantage that it must be measured immediately after etching, and cannot be measured after the formation of various insulating films in subsequent steps.

[Means to solve the problem]

The dimension measurement pattern of the present invention consists of a plurality of lines of the same length each having a minimum design width that requires measurement and a width that is an integral multiple of the minimum design width, and each line has pads for leading out electrodes at both ends. ing.

〔Example〕

FIG. 1 is a plan view of Embodiment 1 of the present invention.

For example, in a gate polysilicon forming process in a semiconductor device manufacturing process, a line 1 having the same dimension as the minimum designed width of gate polysilicon of 1 μm and a line 2 having twice the design width of 2 μm are formed to have the same length of 40 μm, and both ends of each line pattern are There are electrode pads 3a, 3b, 4a, 4 for external extraction.
Place b.

This allows the electrical resistance between the electrode pads 3a and 3b of line 1 and between lines 204a and 4b to be measured in the next or final step.

Here, the design widths of lines 1 and 2 are Ll, L2. i resistance value R
1, R2 and the finished dimension of line 1 is LO, then the finished dimension of the gate polysilicon width which is the same as the width of line 1 can be calculated.

In the first embodiment, the present invention is applied to the gate polysilicon formation process, but it can also be applied to other wiring formation processes, and for example, it is possible to measure thinning or thickening of aluminum wiring.

In addition, in the measurement line, the resistance ratio of two lines with different widths is used in Example 1, but the accuracy can be further improved by forming three or more lines and comparing the resistance values. The longer each line is, the higher the resistance value becomes.
This becomes noticeable when the line becomes thinner or thicker, increasing accuracy.

Therefore, the length is not limited to the length illustrated in Example 1. Further, the widths of line 1 and line 2 are not limited to those in this embodiment, and if the ratio of the line widths is twice or more, there will be no problem in terms of accuracy and it will be easy to calculate an integer multiple.

FIG. 2 is a plan view of Embodiment 2 of the present invention.

The lines 1 and 2 are folded back near the center, and one side of each line is shared by the electrode pad 5. This example has the same area as the first example and approximately twice the line length, which improves measurement accuracy and allows each electrode pad to be placed close to each other, making measurement easier. There are advantages.

〔Effect of the invention〕

As explained above, the present invention has two or more line patterns arranged in the pattern forming process required in the semiconductor device manufacturing process and etched at the same time. By being able to measure and compare the resistance values, it is possible to indirectly measure the etched pattern width.

[Brief explanation of the drawing]

FIG. 1 is a plan view of Embodiment 1 of the present invention. FIG. 2 is a plan view of Embodiment 2 of the present invention. 1...Polysiri line with minimum design width, 2...
...Polysiri line designed with a width twice the minimum width,
3a, 3b, 4a, 4b... Electrode pad, 5.
...Shared pad. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] Dimensional measurement of a mask pattern for photo-etching, characterized in that the pattern has the same length as the required minimum line width and the line width obtained by multiplying the required minimum line width by an integral number, and each pattern has pads for leading out electrodes at both ends. pattern.