JPH0262820U - - Google Patents
Info
- Publication number
- JPH0262820U JPH0262820U JP14172288U JP14172288U JPH0262820U JP H0262820 U JPH0262820 U JP H0262820U JP 14172288 U JP14172288 U JP 14172288U JP 14172288 U JP14172288 U JP 14172288U JP H0262820 U JPH0262820 U JP H0262820U
- Authority
- JP
- Japan
- Prior art keywords
- supplied
- voltage
- amplifier
- rectifier circuit
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第１図は本考案のミユーテイング回路の一実施
例を示す回路図、第２図は第１図に示した実施例
の各部における電圧を示すグラフ、第３図は従来
例を示す図、第４図は第３図に示した従来例の各
部における電圧を示すグラフである。
Ａ１，Ａ２…増幅器、Ｃ１〜Ｃ５…コンデンサ
、Ｄ１…整流ダイオード、Ｄ２，Ｄ３…ダイオー
ド、Ｒ１〜Ｒ７…抵抗、Ｓ…電源スイツチ、Ｔｒ
１…ＰＮＰトランジスタ、Ｔｒ２…ＮＰＮトラン
ジスタ。
FIG. 1 is a circuit diagram showing an embodiment of the muting circuit of the present invention, FIG. 2 is a graph showing voltages at various parts of the embodiment shown in FIG. 1, FIG. 3 is a diagram showing a conventional example, and FIG. The figure is a graph showing voltages at various parts of the conventional example shown in FIG. A1 , A2 ...Amplifier, C1 - C5 ...Capacitor, D1 ...Rectifier diode, D2 , D3 ...Diode, R1 - R7 ...Resistor, S...Power switch, Tr
1 ...PNP transistor, Tr 2 ...NPN transistor.
Claims (1)
インに挿入されたスイツチと、 このスイツチの両端電圧がエミツタに供給され
、このスイツチが閉じたときのみ前記ラインから
の電流がベースに供給されるＰＮＰトランジスタ
と、 このＰＮＰトランジスタのベースに一端が接続
され他端が接地されているコンデンサと、 このＰＮＰトランジスタのコレクタ出力電圧が
ベースに供給され、コレクタの出力電圧により前
記増幅器をミユーテイングするエミツタが接地さ
れたＮＰＮトランジスタとで構成されたことを特
徴とするミユーテイング回路。[Claims for Utility Model Registration] A rectifier circuit that converts an alternating current voltage into a direct current voltage, an amplifier to which the output of the rectifier circuit is supplied, and a switch inserted in a line that supplies the output of the rectifier circuit to the amplifier. , a PNP transistor whose emitter is supplied with voltage across the switch, and a current from the line is supplied to its base only when the switch is closed; one end is connected to the base of this PNP transistor, and the other end is grounded. and an NPN transistor whose base is supplied with the collector output voltage of the PNP transistor and whose emitter is grounded for mutating the amplifier with the collector output voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14172288U JPH0262820U (en) | 1988-10-28 | 1988-10-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14172288U JPH0262820U (en) | 1988-10-28 | 1988-10-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0262820U true JPH0262820U (en) | 1990-05-10 |
Family
ID=31407045
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14172288U Pending JPH0262820U (en) | 1988-10-28 | 1988-10-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0262820U (en) |
-
1988
- 1988-10-28 JP JP14172288U patent/JPH0262820U/ja active Pending