JPH0262824U - - Google Patents
Info
- Publication number
- JPH0262824U JPH0262824U JP14209788U JP14209788U JPH0262824U JP H0262824 U JPH0262824 U JP H0262824U JP 14209788 U JP14209788 U JP 14209788U JP 14209788 U JP14209788 U JP 14209788U JP H0262824 U JPH0262824 U JP H0262824U
- Authority
- JP
- Japan
- Prior art keywords
- output stage
- fet
- gate
- bias circuit
- stage fet
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Tone Control, Compression And Expansion, Limiting Amplitude (AREA)
Description
第１図は本考案の一実施例の回路図、第２図ａ
乃至ｄは第１図の回路における各部の部分的な動
作を説明するための特性図、第３図は第１図の回
路における入力電力―出力電力の特性図、第４図
は従来の増幅回路の一例を示す回路図、第５図ａ
及びｂは第４図の回路における部分的な動作を説
明するための特性図である。
１…入力段ＦＥＴ、２〜４…抵抗、５…ゲート
バイアス入力端子、６…出力段ＦＥＴ、７〜９…
抵抗、１０…ゲートバイアス入力端子、１１，１
２…ゲートバイアス端子、１３…負電源。
Figure 1 is a circuit diagram of an embodiment of the present invention, Figure 2a
d to d are characteristic diagrams for explaining the partial operation of each part in the circuit of Fig. 1, Fig. 3 is a characteristic diagram of input power vs. output power in the circuit of Fig. 1, and Fig. 4 is a conventional amplifier circuit. A circuit diagram showing an example of FIG. 5a
and b are characteristic diagrams for explaining partial operations in the circuit of FIG. 4. 1...Input stage FET, 2-4...Resistor, 5...Gate bias input terminal, 6...Output stage FET, 7-9...
Resistor, 10... Gate bias input terminal, 11, 1
2...Gate bias terminal, 13...Negative power supply.
Claims (1)
ＥＴのゲートに接続されるバイアス回路を備える
多段の増幅器において、出力段ＦＥＴのゲートと
バイアス回路間に直列抵抗を接続し、出力段ＦＥ
Ｔのゲート側を入力段ＦＥＴのバイアス回路に接
続したことを特徴とする増幅回路。 FETs are used in the input stage and output stage, and each FET is
In a multistage amplifier equipped with a bias circuit connected to the gate of the output stage FET, a series resistor is connected between the gate of the output stage FET and the bias circuit, and the output stage FET is connected to the gate of the output stage FET.
An amplifier circuit characterized in that the gate side of the T is connected to a bias circuit of an input stage FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14209788U JPH0262824U (en) | 1988-10-31 | 1988-10-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14209788U JPH0262824U (en) | 1988-10-31 | 1988-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0262824U true JPH0262824U (en) | 1990-05-10 |
Family
ID=31407752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14209788U Pending JPH0262824U (en) | 1988-10-31 | 1988-10-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0262824U (en) |
-
1988
- 1988-10-31 JP JP14209788U patent/JPH0262824U/ja active Pending
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