JPH0262832U - - Google Patents

Info

Publication number
JPH0262832U
JPH0262832U JP14285788U JP14285788U JPH0262832U JP H0262832 U JPH0262832 U JP H0262832U JP 14285788 U JP14285788 U JP 14285788U JP 14285788 U JP14285788 U JP 14285788U JP H0262832 U JPH0262832 U JP H0262832U
Authority
JP
Japan
Prior art keywords
circuit
inputs
output
nand circuit
nand
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14285788U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14285788U priority Critical patent/JPH0262832U/ja
Publication of JPH0262832U publication Critical patent/JPH0262832U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例の回路図、第2図は
本実施例の動作を説明するための波形図、第3図
は従来の単位パルス発生回路の一例の回路図であ
る。 1……スイツチ、2……遅延回路、3……フリ
ツプフロツプ回路、4……微分回路、11,12
……NAND回路、13……AND回路、R1,
R2,R3……抵抗器、C1……コンデンサ、1
4,15……INV回路。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining the operation of this embodiment, and FIG. 3 is a circuit diagram of an example of a conventional unit pulse generation circuit. 1... Switch, 2... Delay circuit, 3... Flip-flop circuit, 4... Differential circuit, 11, 12
...NAND circuit, 13...AND circuit, R 1 ,
R2 , R3 ...Resistor, C1 ...Capacitor, 1
4, 15...INV circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] スイツチからの2つの入力信号の一方を遅延さ
る遅延回路と、この遅延回路からの出力を入力す
る一方のNAND回路と他方の前記入力信号を入
力する他方のNAND回路を有するフリツプフロ
ツプと、前記一方と他方のNAND回路からの出
力の論理積を求めて出力する微分回路とを有する
ことを特徴とする単位パルス発生回路。
A flip-flop has a delay circuit that delays one of two input signals from the switch, one NAND circuit that inputs the output from the delay circuit, and another NAND circuit that inputs the other input signal; 1. A unit pulse generating circuit comprising: a differentiating circuit that calculates and outputs the logical product of the output from the other NAND circuit.
JP14285788U 1988-10-31 1988-10-31 Pending JPH0262832U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14285788U JPH0262832U (en) 1988-10-31 1988-10-31

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14285788U JPH0262832U (en) 1988-10-31 1988-10-31

Publications (1)

Publication Number Publication Date
JPH0262832U true JPH0262832U (en) 1990-05-10

Family

ID=31409161

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14285788U Pending JPH0262832U (en) 1988-10-31 1988-10-31

Country Status (1)

Country Link
JP (1) JPH0262832U (en)

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