JPH026320B2 - - Google Patents
Info
- Publication number
- JPH026320B2 JPH026320B2 JP54119946A JP11994679A JPH026320B2 JP H026320 B2 JPH026320 B2 JP H026320B2 JP 54119946 A JP54119946 A JP 54119946A JP 11994679 A JP11994679 A JP 11994679A JP H026320 B2 JPH026320 B2 JP H026320B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- gain
- pss
- synchronous machine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
- H02P9/00—Arrangements for controlling electric generators for the purpose of obtaining a desired output
- H02P9/14—Arrangements for controlling electric generators for the purpose of obtaining a desired output by variation of field
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Control Of Eletrric Generators (AREA)
Description
【発明の詳細な説明】
本発明は系統安定化装置（以下、PSSと称す
る）に係り、特に同期機の自動電圧調整装置（以
下、AVRと称する）に付加するに好適なPSSに
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a system stabilizing device (hereinafter referred to as PSS), and particularly to a PSS suitable for being added to an automatic voltage regulator (hereinafter referred to as AVR) of a synchronous machine.
一般に、電力系統に接続して運転される同期機
の励磁をAVRによつて同期機の端子電圧が一定
となる様に制御したのでは、同期機の接続される
電力系統と同期機の間の電気機械的電力動揺に対
する制動力があまり得られず安定度が悪くなる。
このため、AVRに同期機の回転子速度Δωや同期
機の端子電圧の周波数ΔF、並びに同期機の入力
または出力電力ΔP等を補助信号として加え、電
力動揺に対する制動力を増し、安定度を向上させ
るためにPSSを付加する方式が、近年電力系統の
安定度向上策の１つとして注目される様になつて
来ている。 Generally, if the excitation of a synchronous machine connected to the power grid and operated is controlled by AVR so that the terminal voltage of the synchronous machine is constant, it is difficult to control the excitation between the power grid to which the synchronous machine is connected and the synchronous machine. Not much braking force can be obtained against electromechanical power fluctuations, resulting in poor stability.
For this reason, the rotor speed Δω of the synchronous machine, the frequency ΔF of the terminal voltage of the synchronous machine, and the input or output power ΔP of the synchronous machine are added to the AVR as auxiliary signals to increase the braking force against power fluctuations and improve stability. In recent years, the method of adding PSS to improve the stability of power systems has been attracting attention as a way to improve the stability of power systems.
第１図はかかる従来のPSSの代表的な回路ブロ
ツク図を示すもので、同図中１はΔω，ΔF，ΔP
等の安定化用信号ａを検出する検出器、２は不完
全微分回路で構成されるシグナルリセツト回路、
３は位相補償回路、４は増幅回路、５は図示しな
いAVRに対して信号ｂを出力するリミツタ回路
である。 Figure 1 shows a typical circuit block diagram of such a conventional PSS, where 1 indicates Δω, ΔF, ΔP.
2 is a signal reset circuit composed of an incomplete differentiation circuit,
3 is a phase compensation circuit, 4 is an amplifier circuit, and 5 is a limiter circuit that outputs a signal b to an AVR (not shown).
かかる構成に於いて、シグナルリセツト回路２
の伝達関数Ｔは
Ｔ＝TSR・Ｓ／（１＋TSR・Ｓ） …(1)
但し、TSRは時定数、Ｓはラプラス演算子、と
いう形で表わされ、その作用は信号の高域周波数
成分を伝達し、低周波成分を取除き、近似的に信
号の定常時からの変化分を取り出すものである。 In such a configuration, the signal reset circuit 2
The transfer function T of It transmits the frequency components, removes the low frequency components, and approximately extracts the change from the steady state of the signal.
一方、位相補償回路３及び増幅回路４は安定化
用信号ａが電力系統の動揺に対して制動効果のあ
る位相と大きさでAVRに加わる様にするもので
あり、リミツタ回路５はPSS出力ｂをある一定値
以内に制限してPSSによる同期機端子電圧の過渡
的な変化を抑制するものである。 On the other hand, the phase compensation circuit 3 and the amplifier circuit 4 ensure that the stabilizing signal a is applied to the AVR at a phase and magnitude that has a damping effect on fluctuations in the power system, and the limiter circuit 5 applies the PSS output b to the AVR. is limited to within a certain value to suppress transient changes in the synchronous machine terminal voltage due to PSS.
いま、安定化用信号ａが通常の電力系統動揺周
波数ωo、通常0.5〜２Hz程度に比較してずつとゆ
つくり変化する場合を考える。この様な例は、発
電機の負荷遮断や系統故障に伴う電力需給の不平
衡により系統周波数がゆつくり変化する場合と
か、揚水発電所に於て起動したポンプ水車に注水
して揚水が開始される場合等に起る。 Now, let us consider a case where the stabilizing signal a gradually changes compared to the normal power system oscillation frequency ω o , which is usually about 0.5 to 2 Hz. Examples of this are when the system frequency changes slowly due to an imbalance in power supply and demand due to generator load shedding or system failure, or when water is injected into a pump-turbine started at a pumped-storage power plant and water pumping begins. This occurs when
この様に、安定化用信号ａが一方向に連続して
変化している時にはPSS出力ｂは一方向にかたよ
り、リミツタ回路５によつて制限された値とな
る。このPSS出力ｂにより同期機端子電圧も
AVRで設定された基準値から一方向に偏倚され、
結局はPSSのリミツタ５の設定値と同じだけ電圧
が上つた状態あるいは下がつた状態となる。その
結果、同期機の界磁電流や電機子電流も定格値を
越えてしまう場合があり、それが長時間継続する
ことは好ましくない。 In this way, when the stabilizing signal a is continuously changing in one direction, the PSS output b is biased in one direction and becomes a value limited by the limiter circuit 5. This PSS output b also causes the synchronous machine terminal voltage to
is biased in one direction from the reference value set by AVR,
Eventually, the voltage will rise or fall by the same amount as the set value of the PSS limiter 5. As a result, the field current and armature current of the synchronous machine may exceed their rated values, and it is undesirable for this to continue for a long time.
更に、この様にPSS出力ｂがリミツタ５にかか
つている状態では電力動揺に制動を与える周波数
成分についても信号が伝達されないのでPSSの効
果が全くなくなつてしまう。 Furthermore, in a state where the PSS output b is applied to the limiter 5 in this manner, no signal is transmitted for the frequency component that dampens the power fluctuation, so the effect of the PSS is completely lost.
第２図の波形図にこの様な状態の一例として
ΔP信号のPSSを装備した同期機の応答を示す。
ちなみに、第２図は水車発電機が出力を増加する
場合の一例を示すもので、横軸は秒を単位とする
時間に対応し、Ａは水車発電機のパーセンテー
ジ、ＢはPSS出力ｂ、Ｃは同期機の端子電圧で
AVRの設定からのずれにそれぞれ対応するもの
である。 The waveform diagram in FIG. 2 shows the response of a synchronous machine equipped with a ΔP signal PSS as an example of such a state.
By the way, Figure 2 shows an example of when a water turbine generator increases its output. The horizontal axis corresponds to time in seconds, A is the percentage of the water turbine generator, B is the PSS output b, and C is the percentage of the water turbine generator. is the terminal voltage of the synchronous machine
This corresponds to each deviation from the AVR settings.
第２図Ａに示す如く、水車発電機は約１分間で
０出力から100％出力まで略々直線的に出力を増
加させている。ΔP信号を安定化信号ａとして用
いるPSSではこの様に同期機出力が変化すると、
この出力変化に応動してPSS出力ｂはリミツタ５
の設定値VLにひつかかつてしまい、第２図Ｂに
示す如く、その値を同期機の出力増加中保持する
こととなる。その結果、同期機の端子電圧は、第
２図Ｃに示す如く、AVRの設定値よりVLだけ下
がつた状態に放置されることとなる。 As shown in FIG. 2A, the water turbine generator increases its output approximately linearly from 0 output to 100% output in about 1 minute. In the PSS that uses the ΔP signal as the stabilization signal a, when the synchronous machine output changes like this,
In response to this output change, PSS output b is set to limiter 5.
As shown in FIG . 2B, this value is maintained while the output of the synchronous machine increases. As a result, the terminal voltage of the synchronous machine is left in a state where it is lower than the set value of the AVR by V L , as shown in FIG. 2C.
これに対して、第１図の如き構成を有するPSS
でこの様な現象を防止するためには、シグナルリ
セツト回路２の時定数TSRを小さくして、同一方
向にゆつくりと変化する信号に対するPSSの出力
を小さくするか、PSSのリミツタ５の設定値を小
さくしてPSSの出力を小さくするか、またはPSS
のゲインを小さく設定して同じ信号に対するPSS
の出力を小さくする等の方法が考えられる。 On the other hand, PSS with the configuration shown in Figure 1
In order to prevent this phenomenon, either reduce the time constant TSR of the signal reset circuit 2 to reduce the PSS output for signals that slowly change in the same direction, or change the setting of the PSS limiter 5. Reduce the value to reduce the output of PSS, or
PSS for the same signal with a smaller gain
Possible methods include reducing the output of
しかしながら、時定数TSRを小さくしてその効
果を十分に出そうとすると時定数TSRが小さくな
り過ぎて制動効果を期待する周波数領域の特性に
も影響を与え通常状態での安定度の向上度合を減
ずることになる。また、リミツタ設定を小さくす
る方法では、通常のわずかな外乱に対してもPSS
出力がリミツタにかかり、PSSの効果を大幅に損
ねてしまう。同様にPSSのゲインを小さくする
と、通常時のPSSの効果を損ねてしまう。 However, if you try to make the time constant T SR small to get the full effect, the time constant T SR will become too small, which will affect the characteristics of the frequency region where the damping effect is expected, making it difficult to improve stability under normal conditions. It will reduce the intensity. In addition, with the method of reducing the limiter setting, PSS
The output will be applied to the limiter, greatly reducing the effectiveness of PSS. Similarly, if the gain of PSS is made small, the effect of PSS during normal operation will be impaired.
従つて、本発明の目的は上記従来技術の欠点を
なくし、安定化用信号が連続して一方向にゆつく
りと変化してゆく場合に、PSS出力が一方向に片
寄り、同期機端子電圧がAVRによる設定値から
長時間外れた状態になることを、常時の効果を損
ねることなく防止すべく、ゲインを出力の状態に
応じて自動的に変更調整し得る新規のPSSを提供
するにある。 Therefore, an object of the present invention is to eliminate the above-mentioned drawbacks of the prior art and, when the stabilizing signal continuously changes slowly in one direction, the PSS output is biased in one direction, and the synchronous machine terminal voltage To provide a new PSS that can automatically change and adjust the gain according to the output state in order to prevent the gain from being deviated from the set value by AVR for a long time without impairing the constant effect. .
以下、図面に従つて本発明を更に詳細に説明す
る。 Hereinafter, the present invention will be explained in more detail with reference to the drawings.
第３図は本発明の一実施例に係るPSSの回路ブ
ロツク図で、同図中６は位相補償回路３の出力を
増幅してリミツタ回路５に与える可変ゲインの増
幅回路、７は前記増幅回路６の出力６ｂを監視
し、状態判別を行う比較回路、８は前記比較回路
７の出力を積分して、その出力８ｂにより前記増
幅回路６のゲインを変化させる積分回路である。 FIG. 3 is a circuit block diagram of a PSS according to an embodiment of the present invention, in which 6 is a variable gain amplifier circuit that amplifies the output of the phase compensation circuit 3 and supplies it to the limiter circuit 5, and 7 is the amplifier circuit. A comparator circuit 8 monitors the output 6b of the comparator circuit 6 to determine the state, and an integrator circuit 8 integrates the output of the comparator circuit 7 and changes the gain of the amplifier circuit 6 based on the output 8b.
かかる構成に於いて、比較回路７は増幅回路６
の出力６ｂが設定値を越えているか否かの検出を
行ない、この状態に応じた信号出力を行なうもの
である。ここで、増幅回路６の出力６ｂが設定値
を越えている時の比較回路７の出力を７ｂ−１、
前記出力６ｂが設定値と等しい時の比較回路７の
出力を７ｂ−０、前記出力６ｂが設定値内にある
時の比較回路７の出力を７ｂ−２とする。 In such a configuration, the comparator circuit 7 is the amplifier circuit 6
It is detected whether or not the output 6b exceeds a set value, and a signal is output in accordance with this state. Here, the output of the comparator circuit 7 when the output 6b of the amplifier circuit 6 exceeds the set value is 7b-1,
The output of the comparison circuit 7 when the output 6b is equal to the set value is 7b-0, and the output of the comparison circuit 7 when the output 6b is within the set value is 7b-2.
そして、積分回路８は前記比較回路７の出力が
７ｂ−２の時に積分値を増加させる方向に動作
し、比較回路７の出力が７ｂ−１の時に積分値を
減少させる方向に動作する。 The integrating circuit 8 operates to increase the integral value when the output of the comparator circuit 7 is 7b-2, and operates to decrease the integral value when the output of the comparator circuit 7 is 7b-1.
一方、増幅回路６は一般に知られている２入力
乗算回路から構成され、その一方の入力には位相
補償回路３の出力を入力し、他方の入力には積分
回路８の出力８ｂを入力する如く構成されるもの
で、その結果、前記増幅回路６の出力６ｂは位相
補償回路３の出力と積分回路８の出力８ｂの両方
に比例することとなる。即ち、増幅回路６は積分
回路８の出力８ｂの大きさに比例したゲインを有
する事になり、可変ゲインの増幅系として動作す
ることとなる。 On the other hand, the amplifier circuit 6 is composed of a generally known two-input multiplier circuit, one input of which receives the output of the phase compensation circuit 3, and the other input of which receives the output 8b of the integration circuit 8. As a result, the output 6b of the amplifier circuit 6 is proportional to both the output of the phase compensation circuit 3 and the output 8b of the integration circuit 8. That is, the amplifier circuit 6 has a gain proportional to the magnitude of the output 8b of the integrating circuit 8, and operates as a variable gain amplifier system.
従つて、通常の運転状態で、増幅回路６の出力
６ｂが比較回路７の設定値を越えていなければ、
比較回路７の出力は７ｂ−２であり、積分回路８
の出力８ｂは増加してその最大値に達する。この
ため、増幅回路６は最もゲインの高い状態で運転
されることとなる。 Therefore, under normal operating conditions, if the output 6b of the amplifier circuit 6 does not exceed the set value of the comparator circuit 7,
The output of the comparator circuit 7 is 7b-2, and the output of the integrator circuit 8 is 7b-2.
The output 8b of increases and reaches its maximum value. Therefore, the amplifier circuit 6 is operated with the highest gain.
次に、増幅回路６の出力６ｂが比較回路７の設
定値を越えると、前記比較回路７の出力は７ｂ−
１となり、積分回路８の出力８ｂは減少する。こ
れに伴つて増幅回路６のゲインも低下し、その出
力６ｂが比較回路７の設定値になるまでゲインは
低下させられる。 Next, when the output 6b of the amplifier circuit 6 exceeds the set value of the comparison circuit 7, the output of the comparison circuit 7 becomes 7b-
1, and the output 8b of the integrating circuit 8 decreases. Along with this, the gain of the amplifier circuit 6 also decreases, and the gain is decreased until the output 6b of the amplifier circuit 6 reaches the set value of the comparator circuit 7.
従つて、通常の運転状態ではPSSとしての効果
が十分発輝される様にシグナルリセツトの時定数
やPSS全体のゲインを選ぶことが可能であり、安
定化信号が連続して一方向に変化してゆくという
様な特殊状態では自動的にPSSのゲインが下げら
れる。その結果、PSSの出力が長時間にわたつて
大きな値となり同期機端子電圧を長時間設定値よ
り外れた値に制御するという様な不具合を除去す
ることが出来る。 Therefore, under normal operating conditions, it is possible to select the time constant of the signal reset and the gain of the entire PSS so that the effect of the PSS is fully realized, and the stabilization signal changes continuously in one direction. In special situations such as when the vehicle is running slowly, the PSS gain is automatically lowered. As a result, it is possible to eliminate a problem in which the output of the PSS becomes large over a long period of time and the synchronous machine terminal voltage is controlled to a value that deviates from the set value for a long period of time.
以上述べた如く、本発明によれば通常状態での
電力動揺等に対する制動効果を損ねることなく、
安定化用信号が連続変化する様な特殊な場合にの
み、系のゲインを下げて、出力の偏倚を防止でき
るPSSを得ることが出来るもので、その有用性極
めて大なるものである。 As described above, according to the present invention, without impairing the braking effect against power fluctuations etc. under normal conditions,
Only in special cases where the stabilizing signal changes continuously, it is possible to obtain a PSS that can prevent output deviation by lowering the gain of the system, and its usefulness is extremely large.
第１図は従来の系統安定化装置の回路ブロツク
図、第２図は第１図の構成の動作の一例を示す波
形図、第３図は本発明の一実施例に係る系統安定
化装置の回路ブロツク図である。
２……シグナルリセツト回路、３……位相補償
回路、４，６……増幅回路、５……リミツタ回
路、７……比較回路、８……積分回路。
FIG. 1 is a circuit block diagram of a conventional system stabilizing device, FIG. 2 is a waveform diagram showing an example of the operation of the configuration shown in FIG. 1, and FIG. 3 is a diagram of a system stabilizing device according to an embodiment of the present invention. FIG. 3 is a circuit block diagram. 2...signal reset circuit, 3...phase compensation circuit, 4, 6...amplifier circuit, 5...limiter circuit, 7...comparison circuit, 8...integrator circuit.
Claims (1)
力及びこれらと等価な信号の少なくとも１個を入
力される入力手段と、前記入力手段の出力信号を
一定の伝達関数で演算処理して同期機の自動電圧
調整手段に印加する処理手段と、前記処理手段に
ゲインを持たせる可変ゲインの増幅手段と、前記
処理手段出力が一定範囲内にある時は前記増幅手
段のゲインを大きくし、逆に一定範囲から外れる
と前記増幅手段のゲインを減少させるゲイン制御
手段とから成ることを特徴とする系統安定化装
置。1. An input means into which at least one of the rotational speed, terminal voltage frequency, electric input/output, and signals equivalent to these of the synchronous machine is input, and the output signal of the input means is processed by a certain transfer function to generate the synchronous machine. a processing means for applying voltage to the automatic voltage adjustment means; a variable gain amplification means for causing the processing means to have a gain; and when the output of the processing means is within a certain range, the gain of the amplification means is increased; A system stabilizing device comprising: gain control means that reduces the gain of the amplification means when the gain falls outside a certain range.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11994679A JPS5644399A (en) | 1979-09-18 | 1979-09-18 | System stabilizing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11994679A JPS5644399A (en) | 1979-09-18 | 1979-09-18 | System stabilizing apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5644399A JPS5644399A (en) | 1981-04-23 |
| JPH026320B2 true JPH026320B2 (en) | 1990-02-08 |
Family
ID=14774084
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11994679A Granted JPS5644399A (en) | 1979-09-18 | 1979-09-18 | System stabilizing apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5644399A (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5586400A (en) * | 1978-12-21 | 1980-06-30 | Mitsubishi Electric Corp | Controller for synchronous machine |
-
1979
- 1979-09-18 JP JP11994679A patent/JPS5644399A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5644399A (en) | 1981-04-23 |
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