JPH0263228A - Burst signal communication equipment - Google Patents

Abstract

PURPOSE:To improve channel utilizing efficiency by providing a reception signal variable control circuit to a digital communication equipment. CONSTITUTION:A data signal S1 demodulated in a demodulator F1 reaches a synchronizing word detection circuit F3 and is transmitted from a reception buffer F2 to an address filter F4 with a signal S2 only when a synchronizing word can be detected. When the content of an address register F5 and an address part of the data signal S1 are coincident with each other in this case, in other words, when the data signal S1 is addressed to its own station, it is sent to a reception signal variable control circuit F6. When some consecutive slots of the data signal S1 are detected, signals S3, S4 controlling the reception of a burst signal are outputted to the demodulator F1 and the reception buffer F2 to obtain a data signal S5 finally. Thus, the utilizing efficiency of the channel is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital communication device, and particularly to a technique for improving channel utilization efficiency when a burst signal has a variable length.

[Conventional technology]

Irrespective of the topological structure of the system, in digital communication systems (e.g., satellite communication systems) where many stations share the same carrier and exchange time-divided busy data (l), the improvement in transmission efficiency can be maximized. This is one of the problems. Conventionally, the slotted Aloha system has been adopted as a solution to this problem. A burst signal communication device for realizing this system is shown in FIG. 3, for example.

Referring to FIG. 3, this device includes a demodulator Fl for demodulating the received signal, a receiving register F2 for temporarily storing the received signal. A synchronization word detection circuit F3 that detects a synchronization word for establishing synchronization between the transmitting side and the receiving side. Address register F that holds the address part of the received signal and the address of the own station
5 and is equipped with an address filter F4 for receiving only the signal sent to the own station.

[Problem to be solved by the invention]

The conventional digital communication device described above can be improved in terms of transmission efficiency. However, signals other than those originally required,
Since the so-called header section occupies a large proportion of the received signal, it has the disadvantage of poor channel utilization efficiency. In other words, apart from the case of a short data signal in a time-sharing system, when the signal spans several kerats, such as a data signal in patch processing, it is necessary to add a header section to each packet. This is extremely wasteful in terms of channel utilization efficiency.

The present invention was made in view of these problems.
The challenge was to adopt the traditional slot Aloha method while
The objective is to increase channel utilization efficiency by adding as little header as possible.

[Means to solve the problem]

The present invention allows multiple stations to share the same carrier.

In digital communication systems that exchange data signals in a time-division manner, especially data signals in patch processing,
A few? When dealing with data signals of up to 100 slots, a signal indicating how many slots are to be used is added to the header section, and a receiver is further provided with a device capable of detecting this signal.

Specifically, the burst signal communication device of the present invention is as follows.

The reception section has a synchronization word detection circuit for detecting a synchronization word in the received signal and an address filter for receiving only the data signal addressed to the own station, and also has a Thereafter, the received signal variable control circuit includes a received signal variable control circuit that detects the header part indicating whether the slots are consecutive, and outputs a signal for controlling the burst signal receiving operation to the demodulator and the receiving buffer, and the received signal variable control circuit It is characterized by being able to receive burst signals under control from the circuit.

〔Example〕

Hereinafter, two embodiments of a digital communication device according to the present invention will be described with reference to the drawings.

FIG. 1 shows an embodiment of a digital communication device according to the present invention. Components that are the same as those of the conventional device shown in FIG. 2 are denoted by the same reference numerals, and explanations thereof will be omitted.

The data signal s1 demodulated by the demodulator FI reaches the synchronization word detection circuit F3, and only if the synchronization word can be detected,
The signal S2 is transmitted from the reception buffer F2 to the address filter F4. Here, the r address register F5
If the content of the data signal S1 matches the address part of the data signal S1, in other words, if the delay signal S1 is intended for the local station, it is transmitted to the received signal variable control circuit F6.

Here, if it is detected that the data signal S1 is busy in several consecutive slots, a signal S3 is sent to the demodulator F1 and the reception buffer F2 to control the burst signal reception operation.
．． By outputting S4, data signal S5 is finally obtained.

〔Effect of the invention〕

As explained above, the present invention provides a digital communication device with a received signal variable control circuit, so that when handling pig signals of several numbers in patch processing, as in the case of short and short data, Since it is only necessary to add a header portion at one location before the data signal, channel utilization efficiency is increased. Therefore, transmission efficiency inevitably increases.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram of an embodiment of a burst signal communication device according to the present invention, FIG. 2 is a configuration diagram of a data signal according to the present invention, and FIG. 3 is a conventional burst signal communication device. It is a block diagram of an example. Fl: demodulator, F2: reception buffer, F3: synchronization word detection circuit, F4 near address filter, F5: address reno star, F6: reception signal variable control circuit. Figure 2

Claims (1)

[Claims] 1. In a burst signal communication device in which the receiving unit has a synchronization word detection circuit for detecting a synchronization word in the received signal and an address filter for receiving only the data signal addressed to the own station, It has a received signal variable control circuit that detects a header section indicating how many consecutive slots the data signal to be received will continue after that, and outputs a signal for controlling the burst signal receiving operation to the demodulator and the receiving buffer. A burst signal communication device, characterized in that burst signals can be received under control from the received signal variable control circuit.