JPH026341U

JPH026341U -

Info

Publication number: JPH026341U
Application number: JP8318988U
Authority: JP
Priority date: 1988-06-23
Filing date: 1988-06-23
Publication date: 1990-01-17

Description

[Brief explanation of drawings]

第１図は本考案の基本的な構成を示すブロツク
図、第２図は本考案の一実施例を示すブロツク図
、第３図は動作の一例を示すタイムチヤートであ
る。１……マイクロプロセツサ、２……主メモリ、
３……未定義命令判定手段、４……命令格納領域
アクセス判定手段、５……停止信号発生手段。 FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart showing an example of the operation. 1...Microprocessor, 2...Main memory,
3... Undefined instruction determining means, 4... Instruction storage area access determining means, 5... Stop signal generating means.

Claims

[Claims for Utility Model Registration] In a microprocessor device consisting of a microprocessor and a main memory for storing instructions to be executed by the microprocessor, an instruction code read from the main memory is input. undefined instruction determining means for determining whether the instruction is a predefined instruction; and instruction storage area access determining means for determining whether the address to the main memory accesses an area in which an instruction is stored. , a signal from the undefined instruction determination means and a signal from the instruction storage area access determination means are input, and the address from the microprocessor accesses an area storing an instruction, and the address from the main memory is A microprocessor device comprising stop signal output means for outputting a signal to stop the operation of the microprocessor if the read instruction is not a predefined instruction.