JPH026359U

JPH026359U -

Info

Publication number: JPH026359U
Application number: JP8200888U
Authority: JP
Priority date: 1988-06-21
Filing date: 1988-06-21
Publication date: 1990-01-17

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例を示す図、第２図
は従来の画像処理装置を示す図である。図におい
て１はラインセンサ、２はラインセンサインタフ
エース、３はマルチポートイメージメモリ、４は
デイスプレイインタフエース、５はデイスプレイ
、６はマルチポート二値メモリ部、７はマルチポ
ートヒストグラムメモリ部、８は固定デイスク装
置、９は固定デイスク装置インタフエース、１０
はフロツピーデイスク装置、１１はフロツピーデ
イスク装置インタフエース、１２はシステムバス
及びイメージバスに接続される高速画像処理プロ
セツサ、１３は制御プロセツサ、１４は操作部、
１５は操作部インタフエース、１６はセンサーバ
ス、１７はデイスプレイバス、１８はリアルタイ
ムバス、１９はシステムバス、２０はイメージバ
ス、２１はシステムバスのみに接続される高速画
像処理プロセツサである。なお図中同一符号は同
一または相当部分を示す。 FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional image processing apparatus. In the figure, 1 is a line sensor, 2 is a line sensor interface, 3 is a multi-port image memory, 4 is a display interface, 5 is a display, 6 is a multi-port binary memory section, 7 is a multi-port histogram memory section, and 8 is a multi-port histogram memory section. Fixed disk device, 9 fixed disk device interface, 10
11 is a floppy disk device, 11 is a floppy disk device interface, 12 is a high-speed image processing processor connected to the system bus and image bus, 13 is a control processor, 14 is an operation unit,
Reference numeral 15 is an operating unit interface, 16 is a sensor bus, 17 is a display bus, 18 is a real-time bus, 19 is a system bus, 20 is an image bus, and 21 is a high-speed image processing processor connected only to the system bus. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

A line sensor that images a subject and outputs an analog video signal; a line sensor interface that creates digitized image data from the analog video signal output from the line sensor;
A multi-port image memory with multiple ports for storing image data, a display interface for creating an image display signal from the image data,
A display that displays an image according to an image display signal output from the display interface, a multi-port binary memory unit having multiple ports that binarizes and stores image data, and a A multi-port histogram memory section with multiple ports for creating and storing horizontal histogram data, a fixed disk device and fixed disk interface for storing various data and programs, and a flowchart for loading programs onto the fixed disk. A high-speed image processing processor that performs high-speed image processing using image data, binary image data, and histogram data; a control processor that controls each of the above components; An operation unit and an operation unit interface that transmit control contents, a sensor bus that transfers image data output from the line sensor interface to the multiport image memory and the multiport binary memory unit, and the multiport image memory. a display bus that transfers image data output from the multi-port image memory to the display interface; a real-time bus that transfers image data output from the multi-port image memory to the multi-port histogram memory section; a system bus for transferring control data and for the high-speed image processing processor to operate the multi-port image memory, the multi-port binary memory section, and the multi-port histogram memory section; and for operating the multi-port binary memory section and the multi-port histogram memory section; and the high-speed image processing processor operating the multi-port image memory, the multi-port binary memory section and the multi-port histogram memory section. An image processing device characterized by comprising an image bus for.