JPH0264255U - - Google Patents

Info

Publication number
JPH0264255U
JPH0264255U JP14352188U JP14352188U JPH0264255U JP H0264255 U JPH0264255 U JP H0264255U JP 14352188 U JP14352188 U JP 14352188U JP 14352188 U JP14352188 U JP 14352188U JP H0264255 U JPH0264255 U JP H0264255U
Authority
JP
Japan
Prior art keywords
signal
receives
modulated
outputs
main amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14352188U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14352188U priority Critical patent/JPH0264255U/ja
Publication of JPH0264255U publication Critical patent/JPH0264255U/ja
Pending legal-status Critical Current

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Landscapes

  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Optical Communication System (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例を示す構成図、第
2図は第1図における各部の波形を示した図、第
3図は従来の光受信器の構成図、第4図は第3図
における各部の波形を示した図であり、1はDC
/DCコンバータ、2はAPD、3は抵抗、4は
プリアンプ、5はメインアンプ、6はD−フリツ
プフロツプ、7はクロツク再生回路、8は光断検
出回路、9はANDゲート、10はデータ信号出
力端子、11はアラーム信号出力端子、12は低
周波信号発生器である。なお、各図中の同一符号
は同一または相当部分を示す。
Fig. 1 is a block diagram showing an embodiment of this invention, Fig. 2 is a diagram showing waveforms of each part in Fig. 1, Fig. 3 is a block diagram of a conventional optical receiver, and Fig. 4 is a block diagram of a conventional optical receiver. 1 is a diagram showing the waveforms of each part in the figure, and 1 is a DC
/DC converter, 2 is an APD, 3 is a resistor, 4 is a preamplifier, 5 is a main amplifier, 6 is a D-flip-flop, 7 is a clock regeneration circuit, 8 is a light disconnection detection circuit, 9 is an AND gate, 10 is a data signal output Terminal 11 is an alarm signal output terminal, and 12 is a low frequency signal generator. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 光信号を電気信号に変換する光受信器において
、光入力信号伝送速度より低い周波数を発生する
交流信号源と、交流信号源より出力された交流信
号を受けて昇圧した直流電圧に前記交流信号を重
ねて出力するDC/DCコンバータと、光信号を
受け、さらに前記DC/DCコンバータの交流信
号を含んだ逆電圧を受けてAM変調された電気信
号を出力するアバランシエホトダイオードと、こ
のアバランシエホトダイオードの一端に接続され
た負荷抵抗と、前記アバランシエホトダイオード
のAM変調化信号を受けて増幅するプリアンプと
、プリアンプにて増幅されたAM変調化信号を受
けてさらに増幅するメインアンプと、メインアン
プにて増幅されたAM変調化信号を受けて偶数倍
クロツク信号を再生するクロツク再生回路と、前
記クロツク信号と、前記メインアンプのAM変調
化出力信号を受けて、前記クロツク信号と同期信
号した出力信号を出力するD−フリツプフロツプ
と、前記メインアンプのAM変調化出力信号を受
けて直流電圧信号として出力する光断検出回路と
、信号断検出回路の出力信号と前記D−FLIP
FLOPの出力信号を受けてAND和として出
力するAND回路とを有する光受信器。
An optical receiver that converts an optical signal into an electrical signal includes an AC signal source that generates a frequency lower than the transmission speed of the optical input signal, and an AC signal output from the AC signal source to convert the AC signal into a boosted DC voltage. A DC/DC converter that outputs in a stacked manner, an avalanche photodiode that receives an optical signal and further receives a reverse voltage containing an alternating current signal from the DC/DC converter and outputs an AM-modulated electric signal, and this avalanche photodiode. A load resistor connected to one end, a preamplifier that receives and amplifies the AM modulated signal of the avalanche photodiode, a main amplifier that receives and further amplifies the AM modulated signal amplified by the preamplifier, and a main amplifier that receives and amplifies the AM modulated signal of the avalanche photodiode. a clock regeneration circuit that receives an AM modulated signal amplified by the clock signal and reproduces an even-numbered clock signal; and an output signal that receives the clock signal and the AM modulated output signal of the main amplifier and is synchronized with the clock signal. a D-flip-flop that outputs an AM modulated output signal of the main amplifier and outputs it as a DC voltage signal;
An optical receiver having an AND circuit that receives an output signal of a FLOP and outputs it as an AND sum.
JP14352188U 1988-11-02 1988-11-02 Pending JPH0264255U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14352188U JPH0264255U (en) 1988-11-02 1988-11-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14352188U JPH0264255U (en) 1988-11-02 1988-11-02

Publications (1)

Publication Number Publication Date
JPH0264255U true JPH0264255U (en) 1990-05-15

Family

ID=31410414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14352188U Pending JPH0264255U (en) 1988-11-02 1988-11-02

Country Status (1)

Country Link
JP (1) JPH0264255U (en)

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