JPH0265334A - Clock recovering circuit for demodulator - Google Patents

Abstract

PURPOSE:To correct clock omission generated by clock extraction by obtaining an OR between a signal is extracted by a clock extracting circuit, and a signal, for which the above mentioned signal is delayed by one period. CONSTITUTION:A demodulating signal inputted from a receiving signal input terminal 1 is inputted to a doubling circuit 2 and after that, the signal is doubled. This doubled signal is inputted to a tank circuit 3 and the signal of a prescribed frequency is extracted from the tank circuit 3. Then, such an extracted signal is inputted to a comparator 4 and waveform is shaped. The output of this comparator 4 is inputted to a delay circuit 5 and the signal of one period-delay is made. This signal of the one period-delay and the output signal of the comparator 4 are inputted to an OR circuit 6. The output of the OR circuit 6 is the clock signal having no clock omission. Namely, even when there is the omission by one clock in the output of the comparator 4, since the one clock just preceding to the omission is outputted from the delay circuit 5 while being delayed by one period, there is no omission in the clock signal synthesized in the OR circuit 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a clock recovery circuit for a demodulator.

[Prior Art] Conventionally, there is a clock recovery circuit shown in FIG. 2 that recovers a clock from this type of demodulated signal.

In this example, the demodulated signal input from the received signal input terminal 1 is input to the 2a multiplication circuit 2, the signal multiplied by 2J is input to the tank circuit 3, and a signal of a predetermined frequency is extracted from the tank circuit 3. A clock output is obtained by inputting the signal to a comparator circuit 4 and performing waveform shaping. The clock output thus obtained is input to the received signal reproducing circuit 7, and is outputted from the demodulated clock output terminal 9. 8 in the figure is a received signal output terminal.

[Problems to be Solved] In the above-described conventional clock regeneration circuit of the demodulator, when received signals come in bursts as in the time division multiplexing system, each burst has a different phase. For this reason, when the electric capacity of the tank circuit 3 that constitutes the clock regeneration circuit is increased, the energy stored in the tank circuit 3 increases, and the release time of the stored energy becomes longer than the rest time between burst signals. . Then,
There is a phenomenon in which the next burst signal casts a shadow on the clock signal to be reproduced, making it impossible to reproduce the clock correctly.

For this reason, conventionally, in order to reduce this influence, the electric capacity of the tank circuit 3 has been lowered to a reasonable value in consideration of the period of the burst signal and the draw-in time of the tank circuit 3. However, as the receiving input electric field decreases, the jitter of the demodulated signal increases, and the jitter of the clock signal also increases, leading to loss of lock as shown in Figure 3 (a). However, there was a drawback that data transmission errors occurred.

The present invention has been made in view of the above-mentioned problems.
An object of the present invention is to provide a clock recovery circuit for a demodulator that can correct clock dropouts that may occur due to clock extraction.

[Means for Solving the Problems] In order to achieve the above object, the clock recovery circuit of the demodulator of the present invention reproduces the clock signal from the demodulated signal by multiplying the demodulated signal by two. A multiplier circuit, a tank circuit that extracts a clock frequency from the output of the multiplier circuit, a comparison circuit connected to the output of the tank circuit, and an output of the comparison circuit that receives the output of the comparison circuit and outputs a one-cycle delayed output. The configuration includes a delay circuit for generating a clock signal, and an OR circuit that inputs the output of the comparison circuit and the output of the delay circuit, and performs a logical sum of the outputs of both circuits to output a clock.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

In addition, below, the common code|symbol is attached|subjected to the part common to the conventional art, and the overlapping description is abbreviate|omitted.

FIG. 1 is a block diagram of an embodiment of the present invention. As shown in FIG. 1, a delay circuit 5 and an OR circuit 6 are interposed between a comparison circuit 4 and a received signal regeneration circuit 7.

In this embodiment as well, the demodulated signal input from the received signal input terminal l is inputted to the double multiplier circuit 2 and then doubled, and this doubled signal is inputted to the tank circuit 3 to output a predetermined signal from the tank circuit 3. This is the same as in the prior art in that a frequency signal is extracted and this extracted signal is input to the comparator circuit 4 for waveform shaping.

Then, the output of this comparison circuit 4 is input to the delay circuit 5, and the third U:i! Create a signal delayed by one period as shown in J(b). Then, this one-cycle delayed signal and the comparator circuit 4
The output signal is input to the OR circuit 6.

The output of the OR circuit 6 becomes a clock signal with no clock omissions as shown in Figure 3 (c). That is, even if there is a drop in the output of the comparator circuit 4 by one clock, the clock immediately preceding the missed clock is output from the delay circuit 5 with a delay of one cycle, so that the clock signal synthesized by the OR circuit 6 There will be no omissions.

[Effects of the Invention] As explained above, the present invention corrects clock omissions caused by clock extraction by calculating the logical sum of a signal extracted by a clock extraction circuit and a signal obtained by delaying that signal by one period. be able to.

This also has the effect of preventing errors in data transmission.

[Brief explanation of the drawing]

The first [1iff is a block diagram of an embodiment of the present invention, the second
The figure is a block diagram of a conventional example, and FIG. 3 is a timing chart showing the timing of each output of the comparison circuit, delay circuit, and OR circuit. 1: Received signal input terminal 2: 25x circuit 3: Tank circuit 4: Comparison circuit 5: Delay circuit 6: OR circuit 7: Received signal regeneration circuit 8: Received signal output terminal 9: Demodulated clock output terminal

Claims (1)

[Claims] A clock regeneration circuit of a demodulator that regenerates a clock signal from a demodulated signal includes a multiplier circuit that doubles the demodulated signal, a tank circuit that extracts a clock frequency from the output of the multiplier circuit, and a tank circuit connected to the output of the tank circuit. a delay circuit that inputs the output of the comparison circuit to produce an output delayed by one period; and a delay circuit that inputs the output of the comparison circuit and the output of the delay circuit, and calculates the logical sum of the outputs of both circuits. 1. A clock regeneration circuit for a demodulator, comprising an OR circuit for outputting a clock signal and outputting a clock signal.