JPH026680Y2 - - Google Patents
Info
- Publication number
- JPH026680Y2 JPH026680Y2 JP13798885U JP13798885U JPH026680Y2 JP H026680 Y2 JPH026680 Y2 JP H026680Y2 JP 13798885 U JP13798885 U JP 13798885U JP 13798885 U JP13798885 U JP 13798885U JP H026680 Y2 JPH026680 Y2 JP H026680Y2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- width
- input signal
- pulse signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000004913 activation Effects 0.000 claims description 6
- 230000002265 prevention Effects 0.000 claims description 2
- 230000001360 synchronised effect Effects 0.000 claims description 2
- 230000000630 rising effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000003111 delayed effect Effects 0.000 description 2
- 244000145845 chattering Species 0.000 description 1
Landscapes
- Arrangements For Transmission Of Measured Signals (AREA)
- Manipulation Of Pulses (AREA)
Description
【考案の詳細な説明】
(産業上の利用分野)
この考案は航空機搭載用機器等における不時作
動防止回路に関する。[Detailed description of the invention] (Industrial field of application) This invention relates to an accidental activation prevention circuit for aircraft-mounted equipment, etc.
(従来の技術)
航空機搭載用機器において誤入力信号等による
機器の不時作動は、重大なる事故につながる恐れ
もあり絶体に避けなければならない。このため、
従来より第3図に示す回路が用いられ接点のチヤ
タリング等による入力ノイズを遮断し正規の入力
信号に変換して機器へ加えていた。第4図のタイ
ムチヤートにより動作を説明する。ワン・シヨツ
ト回路は入力信号a(含ノイズ)の立上りタイミ
ングを検出し、それに同期した、かつR−Cの時
定数により決定される一定幅の負のパルス信号b
を生成する。タイム・デイレイ回路は若干の時間
遅れを生じさせるのであり入力信号aの時間遅れ
信号dを生成する。ワン・シヨツト回路からの負
のパルス信号bと若干の時間遅れ信号dはアンド
回路により論理積演算が行われ、負のパルス出力
の一定幅以内にあるパルス状の入力信号はノイズ
とみなし除去し、図示する出力信号eを生成す
る。すなわち、リレー接点のチヤタリング等によ
るノイズ信号は除去され、またタイム・デイレイ
回路を設けたことにより論理積演算の際のタイミ
ングずれに基づくひげパルス生成等の問題は考え
なくてもよい。(Prior Art) Unintentional activation of aircraft-mounted equipment due to erroneous input signals, etc. may lead to serious accidents and must be avoided at all costs. For this reason,
Conventionally, the circuit shown in FIG. 3 has been used to block input noise caused by contact chatter, etc., convert it into a regular input signal, and apply it to the equipment. The operation will be explained using the time chart shown in FIG. The one-shot circuit detects the rising timing of the input signal a (including noise) and generates a negative pulse signal b that is synchronized with it and has a constant width determined by the time constant of R-C.
generate. The time delay circuit causes a slight time delay and generates a time delay signal d of the input signal a. The negative pulse signal b from the one-shot circuit and the slightly delayed signal d are subjected to an AND operation by an AND circuit, and pulse-shaped input signals within a certain width of the negative pulse output are considered to be noise and removed. , producing the output signal e shown. That is, noise signals caused by chatter of relay contacts, etc. are removed, and since the time delay circuit is provided, there is no need to consider problems such as generation of whisker pulses due to timing deviations during AND operations.
(考案が解決しようとする問題点)
ところで、上記従来例の場合、チヤタリング等
による入力信号の立上り、立下り時のノイズの除
去は容易であるが、入力信号の続行途中における
瞬断(いわばスリツト)は消去できず逆に拡大し
てしまう。すなわち、入力信号aが第5図に示す
ように信号途中で瞬断されスリツトを有する場
合、ワン・シヨツト回路の出力bはスリツトの立
上りタイミングにおいても負のパルス信号を生成
する。従つて、この信号bと入力信号aのタイ
ム・デイレイ回路を経た遅れ信号dとの論理積演
算である出力eは、却つてスリツトが拡げられて
しまう。この結果、機器は入力信号の立上り、立
下り時における不時作動は防止できるが、入力信
号途中での瞬断により入力信号が2回印加された
との判断を行い、信号途中での不時作動は避けら
れない。(Problem to be solved by the invention) By the way, in the case of the above-mentioned conventional example, it is easy to remove the noise at the rise and fall of the input signal due to chattering, etc. ) cannot be deleted and will instead be enlarged. That is, when the input signal a is momentarily interrupted in the middle and has a slit as shown in FIG. 5, the output b of the one-shot circuit generates a negative pulse signal even at the rising timing of the slit. Therefore, the slit of the output e, which is the AND operation of the signal b and the delayed signal d which has passed through the time delay circuit of the input signal a, is rather widened. As a result, the device can prevent unintentional activation at the rise and fall of the input signal, but if there is a momentary interruption in the middle of the input signal, it will be determined that the input signal has been applied twice, and unintentional activation in the middle of the signal will occur. is unavoidable.
(問題点を解決するための手段)
入力信号途中の瞬断によるスリツトを穴埋めす
るとともに立上り、立下り時のノイズを消去し、
航空機搭載用機器に不時作動の恐れをなくすもの
で、従来回路にワン・シヨツト回路とオア回路を
新たに追加するだけの極めて簡易の構成により実
現したことを特徴とする。(Means to solve the problem) Fill in the slits caused by instantaneous interruptions in the middle of the input signal, eliminate noise at the rise and fall,
This eliminates the risk of unintentional activation of equipment mounted on aircraft, and is characterized by an extremely simple configuration that simply adds a one-shot circuit and an OR circuit to the conventional circuit.
第1図にブロツク線図、第2図にタイムチヤー
トを示し、以下具体的に説明する。 A block diagram is shown in FIG. 1, and a time chart is shown in FIG. 2, and a detailed explanation will be given below.
ワン・シヨツト回路Aは入力信号aの立下りタ
イミングを検出し、それに同期したかつR1−C1
の時定数で定まる幅をもつた負のパルス信号bを
生成、次のワン・シヨツト回路Bの入力信号とす
るとともに、その反転信号Cをオア回路の一方の
入力信号とする。ワン・シヨツト回路Bは入力信
号aと先のワン・シヨツト回路Aの一定幅W1を
もつ負のパルス信号bを受けて、入力信号aの立
上りタイミングにあつて、負のパルス信号bがH
レベルのときに、R2−C2時定数により定まる幅
W2の負のパルス信号dを出力する。 One-shot circuit A detects the fall timing of input signal a, and synchronizes it with R 1 −C 1
A negative pulse signal b having a width determined by the time constant of is generated and used as an input signal to the next one-shot circuit B, and its inverted signal C is used as one input signal of the OR circuit. One-shot circuit B receives input signal a and negative pulse signal b with a constant width W1 from previous one-shot circuit A, and at the rising timing of input signal a, negative pulse signal b goes high.
Width determined by R 2 −C 2 time constant at level
Outputs a negative pulse signal d of W2 .
すなわち、このW2幅の負のパルス信号dは入
力信号途中の瞬断によるスリツト立上りでは生成
されなく、スリツトは穴埋めされた形となる。一
方、オア回路はワン・シヨツト回路AのW1幅の
負のパルス信号bの反転信号Cとタイム・デイレ
イ回路を介した入力信号aの論理和演算を行い入
力信号立下り時のノイズ信号を除去し、かつ立上
り時のノイズ信号を略W1幅の正のパルス信号に
変換する。すなわち、ワン・シヨツト回路A,B
の負のパルス信号b,dのパルス幅W1,W2は、
W1+ノイズ信号幅<W2の関係に設定されてお
り、オア回路の出力eとワン・シヨツト回路Bの
W2幅の負のパルス信号dとのアンド回路による
論理積演算は、出力信号fで示すように入力信号
立上り時のノイズ信号の略W1幅正パルス信号が
消去される。すなわち、入力信号の立上り、立下
り時の接点チヤタリング等によるノイズ信号は従
来と同様のワン・シヨツト回路A、タイム・デイ
レイ回路、アンド回路等により除去でき、また入
力信号途中の瞬断によるスリツトはとくにワン・
シヨツト回路Bの作用により穴埋めすることがで
きる。 In other words, this negative pulse signal d having a width of W2 is not generated at the rise of the slit due to a momentary interruption in the input signal, and the slit is in the form of a filled hole. On the other hand, the OR circuit performs a logical OR operation on the inverted signal C of the negative pulse signal b of W1 width of the one -shot circuit A and the input signal a via the time delay circuit, and eliminates the noise signal at the falling edge of the input signal. and converts the noise signal at the rising edge into a positive pulse signal with a width of approximately W1 . That is, one-shot circuits A and B
The pulse widths W 1 and W 2 of the negative pulse signals b and d are,
The relationship is set as W 1 + noise signal width < W 2 , and the output e of the OR circuit and the one-shot circuit B
In the logical product operation by the AND circuit with the negative pulse signal d having a width of W 2 , as shown by the output signal f, the approximately W 1 width positive pulse signal of the noise signal at the rising edge of the input signal is eliminated. In other words, noise signals caused by contact chatter at the rise and fall of the input signal can be removed by the conventional one-shot circuit A, time delay circuit, AND circuit, etc., and slits caused by instantaneous interruptions in the middle of the input signal can be removed. Especially one
The hole can be filled by the action of shot circuit B.
(作用)
2つのワン・シヨツト回路を用いて幅値を異に
するパルス出力を生成、入力信号立上り、立下り
時のノイズ信号とともに入力信号途中の瞬断によ
るスリツトにおいても上記一定幅の間出力を一定
値に維持しかつこれら一定幅の出力を論理演算し
てノイズ信号、スリツトを除去するようにした。(Function) Two one-shot circuits are used to generate pulse outputs with different width values, and the pulse outputs are output for the above constant width even when there is a noise signal at the rise and fall of the input signal, as well as a slit caused by a momentary interruption in the input signal. is maintained at a constant value, and the outputs having a constant width are subjected to logical operations to remove noise signals and slits.
(考案の考案)
従来のものに、ワン・シヨツト回路とオア回路
を新たに加えるだけの簡易の回路構成で、入力信
号途中の瞬断によるスリツトをも消去することが
でき、入力信号の立上り、立下り時のノイズ信号
の除去とも相まつて、入力信号に含まれるノイズ
の除去は完全であり、航空機搭載用機器等の不時
作動を防止することができる。(Inventive idea) With a simple circuit configuration that simply adds a one-shot circuit and an OR circuit to the conventional one, it is possible to eliminate slits caused by instantaneous interruptions in the middle of the input signal, and to eliminate Coupled with the removal of the noise signal at the time of falling, the noise contained in the input signal is completely removed, making it possible to prevent unintentional operation of aircraft-mounted equipment and the like.
図面は、第1図が本考案実施例のブロツク線
図、第2図はその動作を説明するためのタイムチ
ヤート、第3図が従来例のブロツク線図、第4
図、第5図がその動作を説明するためのタイムチ
ヤートである。
ONE・SHOTA……ワン・シヨツト回路、
ONE・SHOTB……ワン・シヨツト回路B、OR
……オア回路、AND……アンド回路。
As for the drawings, Fig. 1 is a block diagram of the embodiment of the present invention, Fig. 2 is a time chart for explaining its operation, Fig. 3 is a block diagram of the conventional example, and Fig. 4 is a block diagram of the embodiment of the present invention.
FIG. 5 is a time chart for explaining the operation. ONE SHOTA……One shot circuit,
ONE・SHOTB……One shot circuit B, OR
...OR circuit, AND...AND circuit.
Claims (1)
期して、幅W1のパルス信号を生成するワン・シ
ヨツト回路Aと、上記W1幅のパルス信号及び入
力信号を受けこのW1幅パルス信号のHレベルの
間における入力信号の立上りタイミングに同期し
かつW1幅より広いW2幅のパルス信号を生成する
ワン・シヨツト回路Bと、入力信号の、タイム・
デイレイ回路を介し若干のタイムラグを持たせた
信号と先のW1幅パルス信号の論理和演算を行う
オア回路と、この演算結果と先のW2幅パルス信
号の論理積演算を行うアンド回路、を備え、この
アンド回路出力を出力信号として用いるようにし
たことを特徴とする不時作動防止回路。 A one-shot circuit A detects the fall timing of an input signal and generates a pulse signal with a width of W 1 in synchronization with it, and receives the above-mentioned pulse signal with a width of W 1 and the input signal and generates the H of the W 1- width pulse signal. A one-shot circuit B that generates a pulse signal with a width of W2 which is wider than the width of W1 and which is synchronized with the rise timing of an input signal between levels;
An OR circuit that performs an OR operation between a signal with a slight time lag via a delay circuit and the previous W 1 -width pulse signal, an AND circuit that performs an AND operation between this operation result and the previous W 2 -width pulse signal, What is claimed is: 1. An unintentional activation prevention circuit characterized in that the AND circuit output is used as an output signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13798885U JPH026680Y2 (en) | 1985-09-09 | 1985-09-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13798885U JPH026680Y2 (en) | 1985-09-09 | 1985-09-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6247230U JPS6247230U (en) | 1987-03-23 |
| JPH026680Y2 true JPH026680Y2 (en) | 1990-02-19 |
Family
ID=31042555
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13798885U Expired JPH026680Y2 (en) | 1985-09-09 | 1985-09-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH026680Y2 (en) |
-
1985
- 1985-09-09 JP JP13798885U patent/JPH026680Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6247230U (en) | 1987-03-23 |
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