JPH0267444U - - Google Patents
Info
- Publication number
- JPH0267444U JPH0267444U JP14524788U JP14524788U JPH0267444U JP H0267444 U JPH0267444 U JP H0267444U JP 14524788 U JP14524788 U JP 14524788U JP 14524788 U JP14524788 U JP 14524788U JP H0267444 U JPH0267444 U JP H0267444U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- cpu
- wait
- nmi
- synchronous
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 238000012544 monitoring process Methods 0.000 description 1
Landscapes
- Information Transfer Systems (AREA)
Description
第１図は本考案を実施した同期制御回路の構成
概念図、第２図は本考案回路の実際の回路構成図
、第３図及び第４図は本考案回路の動作を表わす
タイムチヤート、第５図は本考案を実施した他の
例を表わす構成図、第６図は従来の同期型ＣＰＵ
の動作を表わすタイムチヤートである。
１……同期型ＣＰＵ、２……メモリまたはＩ／
Ｏ、３……ウエイト信号発生部、４……ＮＭＩ信
号発生部、５……アドレス・デコーダ、６……監
視回路、７……クロツク・ドライバ、ＦＦ１，Ｆ
Ｆ２……フリツプ・フロツプ回路、Ｇ１，Ｇ２…
…ゲート回路。
Figure 1 is a conceptual diagram of the configuration of a synchronous control circuit implementing the present invention, Figure 2 is an actual circuit diagram of the circuit of the present invention, and Figures 3 and 4 are time charts showing the operation of the circuit of the present invention. Figure 5 is a block diagram showing another example implementing the present invention, and Figure 6 is a conventional synchronous CPU.
This is a time chart showing the operation. 1...Synchronous CPU, 2...Memory or I/
O, 3...Wait signal generation section, 4...NMI signal generation section, 5...Address decoder, 6...Monitoring circuit, 7...Clock driver, FF1, F
F2...Flip-flop circuit, G1, G2...
...Gate circuit.
Claims (1)
置され、前記同期型ＣＰＵから発せられるアクセ
ス要求信号から生成され前記メモリまたはＩ／Ｏ
からのアクノリツジ信号で解除されるウエイト信
号を発生するウエイト信号発生部と、前記アクノ
リツジ信号が返つてこないことを検出してＮＭＩ
（Ｎｏｎ−Ｍａｓｋａｂｌｅ Ｉｎｔｅｒｒｕｐ
ｔ）信号を前記ＣＰＵに与えるＮＭＩ発生部とを
有すること特徴とする同期制御回路。 installed between a synchronous CPU and a memory or I/O, and generated from an access request signal issued from the synchronous CPU;
a wait signal generator that generates a wait signal that is canceled by an acknowledge signal from the NMI; and a wait signal generator that detects that the acknowledge signal is not returned
(Non-Maskable Interrupt
t) an NMI generation section that provides a signal to the CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14524788U JPH0267444U (en) | 1988-11-07 | 1988-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14524788U JPH0267444U (en) | 1988-11-07 | 1988-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0267444U true JPH0267444U (en) | 1990-05-22 |
Family
ID=31413673
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14524788U Pending JPH0267444U (en) | 1988-11-07 | 1988-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0267444U (en) |
-
1988
- 1988-11-07 JP JP14524788U patent/JPH0267444U/ja active Pending
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