JPH0268533U - - Google Patents

Info

Publication number
JPH0268533U
JPH0268533U JP14674488U JP14674488U JPH0268533U JP H0268533 U JPH0268533 U JP H0268533U JP 14674488 U JP14674488 U JP 14674488U JP 14674488 U JP14674488 U JP 14674488U JP H0268533 U JPH0268533 U JP H0268533U
Authority
JP
Japan
Prior art keywords
circuit
output signal
signal
level
intermediate frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14674488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14674488U priority Critical patent/JPH0268533U/ja
Publication of JPH0268533U publication Critical patent/JPH0268533U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Superheterodyne Receivers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例による中間周波信
号処理回路およびFMフロントエンドの構成を示
すブロツク図である。 3……狭帯域中間周波増幅回路、4……広帯域
中間周波増幅回路、5,6……FM検波回路、7
……信号レベル・位相調整回路、8……信号レベ
ル調整回路、9,13……差動増幅回路、10…
…妨害信号レベル検出回路、11……妨害信号レ
ベル調整回路、12……スイツチ。
FIG. 1 is a block diagram showing the structure of an intermediate frequency signal processing circuit and an FM front end according to an embodiment of the invention. 3... Narrowband intermediate frequency amplification circuit, 4... Wideband intermediate frequency amplification circuit, 5, 6... FM detection circuit, 7
...Signal level/phase adjustment circuit, 8...Signal level adjustment circuit, 9, 13...Differential amplifier circuit, 10...
... Interference signal level detection circuit, 11 ... Interference signal level adjustment circuit, 12 ... Switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 狭帯域中間周波増幅回路と、広帯域中間周波増
幅回路と、前記狭帯域中間周波増幅回路の出力信
号を検波する第1の検波回路と、前記広帯域中間
周波増幅回路の出力信号を検波する第2の検波回
路と、前記第1の検波回路の出力信号のレベルお
よび位相を調整する信号レベル・位相調整回路と
、前記第2の検波回路の出力信号のレベルを調整
する信号レベル調整回路と、反転入力端子に前記
信号レベル・位相調整回路の出力信号が入力され
、非反転入力端子に前記信号レベル調整回路の出
力信号が入力される第1の差動増幅回路と、前記
第1の差動増幅回路の出力信号に含まれている妨
害信号のレベルを検出する妨害信号レベル検出回
路と、前記第1の差動増幅回路の出力信号に含ま
れている妨害信号のレベルを調整する妨害信号レ
ベル調整回路と、前記妨害信号レベル検出回路の
出力信号によつてオン、オフされ、前記妨害信号
レベル調整回路の出力信号を通過させるスイツチ
と、反転入力端子が前記スイツチと接続され、非
反転入力端子に前記信号レベル調整回路の出力信
号が入力される第2の差動増幅回路とを具備する
ことを特徴とする中間周波信号処理回路。
a narrowband intermediate frequency amplification circuit, a wideband intermediate frequency amplification circuit, a first detection circuit that detects an output signal of the narrowband intermediate frequency amplification circuit, and a second detection circuit that detects an output signal of the wideband intermediate frequency amplification circuit. a detection circuit, a signal level/phase adjustment circuit that adjusts the level and phase of the output signal of the first detection circuit, a signal level adjustment circuit that adjusts the level of the output signal of the second detection circuit, and an inverting input. a first differential amplifier circuit into which the output signal of the signal level/phase adjustment circuit is input to a terminal and the output signal of the signal level adjustment circuit is input to a non-inverting input terminal; and the first differential amplifier circuit. an interfering signal level detection circuit that detects the level of an interfering signal contained in the output signal of the first differential amplifier circuit; and an interfering signal level adjustment circuit that adjusts the level of the interfering signal contained in the output signal of the first differential amplifier circuit. a switch that is turned on and off by the output signal of the interference signal level detection circuit and passes the output signal of the interference signal level adjustment circuit; an inverting input terminal is connected to the switch; An intermediate frequency signal processing circuit comprising: a second differential amplifier circuit to which an output signal of the signal level adjustment circuit is input.
JP14674488U 1988-11-10 1988-11-10 Pending JPH0268533U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14674488U JPH0268533U (en) 1988-11-10 1988-11-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14674488U JPH0268533U (en) 1988-11-10 1988-11-10

Publications (1)

Publication Number Publication Date
JPH0268533U true JPH0268533U (en) 1990-05-24

Family

ID=31416521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14674488U Pending JPH0268533U (en) 1988-11-10 1988-11-10

Country Status (1)

Country Link
JP (1) JPH0268533U (en)

Similar Documents

Publication Publication Date Title
JPH02817U (en)
JPH01139617U (en)
JPS62168163U (en)
JPH03130641U (en)
JPS6397918U (en)
JPH0286217U (en)
JPS63102339U (en)
JPH01153785U (en)
JPS62188827U (en)
JPH0438120U (en)
JPS61195113U (en)
JPS62173812U (en)
JPS63106212U (en)
JPH0244432U (en)
JPH0236237U (en)
JPH01126622U (en)
JPS6241200U (en)
JPS62181024U (en)
JPH0163232U (en)
JPH048528U (en)
JPH02134725U (en)
JPS6423119U (en)
JPS628724U (en)
JPH02130199U (en)
JPS61166641U (en)