JPH0268542U - - Google Patents

Info

Publication number
JPH0268542U
JPH0268542U JP14709588U JP14709588U JPH0268542U JP H0268542 U JPH0268542 U JP H0268542U JP 14709588 U JP14709588 U JP 14709588U JP 14709588 U JP14709588 U JP 14709588U JP H0268542 U JPH0268542 U JP H0268542U
Authority
JP
Japan
Prior art keywords
baud rate
clk
signal
rate clk
generation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14709588U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14709588U priority Critical patent/JPH0268542U/ja
Publication of JPH0268542U publication Critical patent/JPH0268542U/ja
Pending legal-status Critical Current

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Landscapes

  • Communication Control (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示すブロツク図、
第2図a〜cは第1図に示すシリアルデータ受信
器の入力信号の波形図、第3図は従来の一例を示
すブロツク図である。 1……データ受信回路、2……微分回路、3…
…ボーレートCLK発生回路、4……コマンドデ
ーコーダ回路、a1……変調信号、a2……デー
タ信号、a3……データ信号、b1……制御信号
、c1……ボーレートCLK信号、PO……入力
ポート。
FIG. 1 is a block diagram showing an embodiment of the present invention.
2a to 2c are waveform diagrams of input signals of the serial data receiver shown in FIG. 1, and FIG. 3 is a block diagram showing a conventional example. 1...Data receiving circuit, 2...Differentiating circuit, 3...
...Baud rate CLK generation circuit, 4...Command decoder circuit, a1...Modulation signal, a2...Data signal, a3...Data signal, b1...Control signal, c1...Baud rate CLK signal, PO...Input port .

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] データ信号に制御信号を重畳させて変調した変
調信号を受信し復調して前記データ信号を出力す
るデータ受信回路と、前記変調信号を受信し微分
して前記制御信号を出力する微分回路と、CLK
信号の周波数に応じてボーレートCLK信号を出
力するボーレートCLK発生回路とを含む事を特
徴とするシリアルデータ受信器。
CLK
A serial data receiver comprising: a baud rate CLK generation circuit that outputs a baud rate CLK signal according to the frequency of the signal.
JP14709588U 1988-11-11 1988-11-11 Pending JPH0268542U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14709588U JPH0268542U (en) 1988-11-11 1988-11-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14709588U JPH0268542U (en) 1988-11-11 1988-11-11

Publications (1)

Publication Number Publication Date
JPH0268542U true JPH0268542U (en) 1990-05-24

Family

ID=31417187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14709588U Pending JPH0268542U (en) 1988-11-11 1988-11-11

Country Status (1)

Country Link
JP (1) JPH0268542U (en)

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