JPH0268637A - Supervisory and controlling equipment for microcomputer - Google Patents

Abstract

PURPOSE:To surely execute the supervisory and control of a microcomputer with a simple constitution by constituting the title equipment in such a manner that an output signal generated when a overflow occurs in a watchdog counter is coupled in wired-OR with a reset signal from a power source reset device as a reset command, and it is supplied to the microcomputer. CONSTITUTION:The equipment is constituted so that a power source reset signal to initialize and reset the microcomputer in a specific time range at the time of applying a power source can be generated, and a watchdog clear signal generated from the microcomputer is supplied to a supervisory device 25, thereby, the reset control of the watchdog counter 31 is performed. The watchdog counter 31 detects abnormality in the microcomputer corresponding to the overflow, and a detecting signal is taken out via an inverter 16 of open- drain, and is coupled with the power source rest signal with the wired-OR and is supplied to the microcomputer. In such a manner, abnormality decision is issued only in an abnormal state where no watchdog clear signal is generated from the microcomputer, which improves reliability for the device.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention is applicable to a vehicle engine control, for example, in which an initial reset state is set when power is turned on, and reset control is performed when an abnormal state is detected. The present invention relates to a microcomputer monitoring and control device used in applications such as microcomputer monitoring and control.

[Prior Art] For example, a microcomputer is used as an engine control device for a vehicle, and this microcomputer controls the amount of fuel injected in accordance with the operating conditions of the engine, the timing of fuel injection, and the timing of ignition. Electronic controls such as these are used.

If an abnormality occurs in a microcomputer used for engine control, etc.,
Immediately stop controlling this microcomputer,
It is necessary to switch to a backup means that does not use a microcomputer so that fuel injection timing, ignition timing, etc. can be controlled by this backup means.

For this reason, it is necessary to constantly monitor the operating state of the microcomputer, and as a means for such monitoring, a program runaway detection method is known, for example, as disclosed in Japanese Patent Application Laid-Open No. 60-27038. There is. In this method, a watchdog timer is used as a runaway detection circuit for the microprocessor. A static circuit is set in the microprocessor, and when the microprocessor is reset, the watchdog timer is prohibited from operating. When the processor first accesses the watchdog timer, the inhibited state is released, and the watchdog's operation is not inhibited until the microprocessor is reset next time.

However, if a static circuit is set up in the microprocessor in this way, for example, if the microprocessor goes out of control and you try to reset the microprocessor using the output from the watchdog timer, the reset signal from the watchdog timer will be reset. output terminal and
A prohibition command input terminal for prohibiting the operation of the watchdog timer when a reset command is issued to the microprocessor and a prohibition circuit for disabling the operation of the watchdog timer in response to this human input signal are required. Significantly more complex.

As a means to counter this problem, there is a power supply reset device that sets the initial reset state of the microcomputer within a specified time range in the initial state when the power is turned on;
and a monitoring device equipped with a watchdog counter whose reset is controlled by a watchdog clear signal from the microcomputer, and the signal from the power supply reset device and the reset signal from the monitoring device are combined by a wired OR, and It is conceivable to have it supplied.

FIG. 4 shows the configuration of a monitoring device used in such a case, and is equipped with an edge detection circuit 11 to which a watchdog clear signal generated during normal operation is supplied to a microcomputer (not shown). circuit 11
When a rising or falling edge of the watchdog clear signal is detected, a reset command is given to the watchdog counter 12.

The watchdog counter counts the clock signal, and the overflow signal is D driven by the clock signal.
A type flip-flop 13 is supplied.

The output signal from this D-type flip-flop 13 is outputted via an oven-drain inverter 14, combined with the signal from the power reset device by wired OR, and supplied to the microcomputer to be monitored. It is.

That is, when the power is turned on at time I as shown in (A) in Figure 5, the signal from the power reset device becomes as shown in (B) in the same figure, and is supplied to the microcomputer at time (2). The reset signal generated rises. Therefore, as shown in (C) of the same figure, the microcomputer starts operating from the time point (3) when the power reset is released, and a watchdog clear signal is generated periodically, so that the watchdog counter 12 is reset by this clear signal. In this case, the reset command signal supplied to the microcomputer is the same as the signal from the power supply reset circuit, regardless of the output from the monitoring device, since the signal from the power supply reset circuit rises at time point ■ as shown in figure (B). The result is as shown in (D) of the figure. That is, the output of this monitoring device is obtained from an inverter with an open drain configuration, and this output signal is obtained from the (B
) This is because the signal shown in the figure is supplied to the microcomputer by a wired OR.10 The monitoring device uses a low voltage such that the microcomputer is stopped in order to back up the output of the microcomputer. It is configured to operate in any condition. Therefore, even while the microcomputer is in the initial reset state, it continues to operate, and the watchdog counter 12 continues to perform counting operations. In this case, if this counter 12 is driven in a free-run manner, its counting state will be the fifth.
As shown in (E) of the figure, at the time (3) when this counter 12 overflows, this monitoring device determines that there is an abnormality in the microcomputer.

In this way, when an abnormality is determined and the backup function is activated, the microcomputer begins to generate a watchdog clear signal at point (3), and at this point (2) the watchdog counter 12 is reset and determined to be normal.

That is, after the microcomputer was determined to be abnormal, it was determined to be normal, which was a problem due to the backup control of the microcomputer.

[Problems to be Solved by the Invention] This invention has been devised in view of the following two points.It is an object of the present invention to provide a sufficiently simple structure to reliably detect an abnormal state of a microcomputer. An object of the present invention is to provide a microcomputer monitoring and control device that prevents a contradiction in which an abnormality is detected in the microcomputer in an initial power reset state and a normality determination is made after the power reset state is released. It is.

[Means for Solving the Problems] In the microcomputer monitoring and control device according to the present invention, a power supply reset signal is generated for initially resetting the microcomputer within a specific time range when the power is turned on, and A watchdog clear signal generated from the microcomputer is supplied to the monitoring device to control the reset of the watchdog counter.

This watchdog counter detects an abnormality in the microcomputer in response to an overflow. This detection signal is taken out via the oven drain inverter, combined with the above power supply reset signal by wired OR, and supplied to the microcomputer. . Then, the power supply reset signal is detected by the output section from the monitoring device, and the watchdog counter is reset when the power supply is reset.

[Function] In the microcomputer monitoring and control device configured as described above, in the initial reset state of the power supply,
A watchdog counter constituting the monitoring device is maintained in a reset state by the presence of the power supply reset signal. Therefore, in this power reset state, the watchdog counter will not overflow and the microcomputer will not be judged to be abnormal.
For example, there is no need to back up microcomputers. An abnormality is determined only when the microcomputer is in an abnormal operating state in which no watchdog clear signal is generated from the microcomputer, and the reliability of various electronic control devices using microcomputers is greatly affected. will be improved.

[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows its configuration. A microcomputer 21 performs electronic control of, for example, an automobile engine. In other words, although the details are not shown, the operating state of the engine is detected, the fuel injection amount, fuel injection timing, ignition timing, etc. are calculated based on this detection signal, and the fuel amount control, injection timing, and ignition are performed according to the calculation results. This is to control the timing.

Power is supplied to the microcomputer 21 in response to commands from a power reset device 22, and when an engine control device is configured, a battery power supply is connected to the microcomputer 21 via an ignition switch 23. Power is supplied from 24.

Microcomputer 2! From this, a watchdog clear signal is generated at short intervals when power is supplied and the watchdog is operating normally, and this watchdog clear signal is supplied to the monitoring device 25. This monitoring device 25
Operating power is supplied via a power supply circuit consisting of a resistor R and a capacitor C, and power is supplied, for example, in response to turning on the ignition switch 25, although details are not shown.

The monitoring device 25 generates a low-level reset signal in response to detection of an abnormal state in the microcomputer 21, and this reset signal is supplied to the microcomputer 21 by a wired OR together with a power reset signal from the power reset device 22. Ru. In addition, the monitoring device 25 sends a signal to the base of the transistor 26 when an abnormality is detected, lights up the warning lamp 27, and
Although not shown in the figure, an operation command is given to a backup device for fuel injection timing and ignition timing control.

FIG. 2 shows the monitoring device 25 in detail.
It includes a watchdog counter 3L that is driven by a clock signal and an edge detection circuit 32 that is supplied with a watchdog clear signal from the microcomputer 21. This edge detection circuit 32 detects the rising edge or falling edge of each pulsed watchdog clear signal generated when the microcomputer 21 is operating normally, and this edge detection signal is passed through an OR gate 33. and is supplied to the reset terminal R of the watchdog counter 31.

The watchdog counter 31 generates a high-level output signal when the count value overflows, and the overflow signal from the watchdog counter 31 is supplied to the D terminal of the D-type flip-flop 34. A clock signal for driving the watchdog counter 31 is supplied to this flip-flop 34 as a driving signal via an inverter 35, and after 1/2 clock period after the watchdog counter 31 overflows, the clock signal is output. The signal from Q rises to high level.

The output signal from this flip-flop 34 is supplied to an inverter 36 having an oven-drain structure, and the output of this inverter 36 is coupled with a power reset signal from the Tu source reset circuit 22 and the like by a wired OR.

In this case, the power reset device 22 has an oven collector structure, and if either the output of the power reset device 22 or the output of the inverter 36 is at a low level, the microcomputer 21 is reset. It looks like this.

Further, the output terminal section of the inverter 3G is connected to the OR gate 33 via the inverter 37, and the monitoring device 2
The watchdog counter 31 is kept in a reset state when the output terminal section of the output terminal 5 is at a low level.

That is, since the inverter 36 is configured with an oven drain, when the output of the flip-flop 34 is at a low level (the counter 31 is not overflowing), the output of the inverter 34 is in the oven state (via the pull-up resistor). (high level when voltage is applied). Therefore, when the output from the power supply reset device 22 is at a low level, the human power of the inverter 37 is at a low level, and a reset command is given to the watchdog counter 31 via the OR gate 33.

” In a device configured like two legs, when the ignition switch 23 is turned on at time I, the power supplied to the power reset device 22 is turned on at time I as shown in FIG. 3(a). Go up. The power supplied from the power supply reset device 22 to the microcomputer 21 becomes high level at the time (3) when a predetermined initial reset period has elapsed, as shown in FIG. 3(b). In this case, the power supply of the monitoring device 25 starts up as shown in FIG. 3(c) with a time constant set by the resistor R and the capacitor C from the time when the ignition switch 23 is turned on.

In the microcomputer 21, even when the power is turned on, it is in a clean reset state until point ①, so no watchdog clear signal is generated, and after the initial reset period has elapsed, power is applied and it operates normally. When it comes to the state,
As shown in FIG. 3(d), the period is sufficiently shorter than the overflow period of the watchdog counter 31.
Generates a pulsed watchdog clear signal.

Further, when the watchdog counter 31 does not overflow, the output of the flip-flop 13 is at a low level, and in this state, the output of the inverter 3G is in an open state. Therefore, when the power supply of the microcomputer 21 is in the initial reset period and the power supply voltage is at the low level as shown in FIG. The output of the inverter 37 becomes a high level, and the watchdog counter 31 is held in a reset state until time point (2).

However, after the point (3) when the 71i source reset state ends, the output stage of the power supply reset device 22 is also in an open state, and is set to a high level by a pull-up resistor (not shown), and the reset state of the watchdog counter 31 is released.

(f) in FIG. 3 shows the counting state of the watchdog counter 31 controlled as described above.
Until then, the stopped state with no counting operation is maintained until time H
After the elapse of , a counting operation is performed by the clock. This counting operation is cleared by a watchdog clear signal from the microcomputer 21. When the microcomputer 21 is operating normally, the watchdog counter 31 will not overflow and the flip-flop 34 will not overflow. The output of (g
) is kept at a low level as shown in ( ).

Here, the signal applied to the base of the transistor 2G is taken out from the output side of the flip-flop 34, for example, and when the output of the flip-flop 34 becomes a high level, that is, the microcomputer 21 becomes abnormal and the watchdog is cleared. When no signal is generated and the watchdog counter 3I overflows, it becomes high level. Therefore, when the microcomputer 21 is operating normally, the base of the transistor 26 is at a low level, and the collector potential of the transistor 26 becomes as shown in FIG. has been done.

When an abnormal state is detected in the microcomputer 21, the lamp 27 is turned on to notify the abnormality.At the same time, although not particularly shown in this figure,
For example, operation commands are issued to backup means for fuel injection timing control and ignition timing control. This abnormal pressure detection state is canceled by an output signal from the edge detection circuit 32, for example.

[Effects of the Invention] As described above, in the microcomputer monitoring and control device according to the present invention, the watchdog counter, which is reset-controlled by the watchdog clear signal from the microcomputer, is in the stopped state in the initial reset state of the power supply. During this period, an overflow occurs and no abnormality is detected even though the microcomputer is normal. Then, after the initial reset period of the power supply ends, the microcomputer starts monitoring, and the control of, for example, the backup device etc. is executed smoothly.

In particular, the above device allows the output terminal section of the monitoring device to be used as a human power source for resetting the watchdog counter without adding any special circuit configuration. Supervisory control is reliably executed, and the effect is remarkable when applied to, for example, a microcomputer for electronic control of an automobile engine.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating a microcomputer monitoring and control device according to an embodiment of the present invention, and FIG. 2 shows the monitoring device section of the above-mentioned device (1 is the origin, and FIG. 3 is the above-mentioned A time chart explaining the operation of the device, FIG. 4 is a configuration diagram explaining the conventional view control device,
FIG. 5 is a time chart illustrating the operating state of the above device. 21... Microcomputer, 22... Power supply resent device (output stage has oven collector structure), 23...
・Ignition switch, 24... battery power supply,
25... Monitoring device, 27... Lamp, 31... Watchdog counter, 32... Edge detection circuit, 3
4...D type flip-flop, 3G...impeller with open drain structure. Applicant's agent Patent attorney Takehiko Suzue Figure 3 Figure 1 Figure 2 Figure 4 Figure 5

Claims (1)

[Claims] A power supply reset device that maintains a microcomputer to be monitored in a reset state for a time range specified in the initial state after power is turned on, and then sets an operating power supply; a monitoring device that monitors a watchdog clear signal generated by the watchdog clear signal, and generates a reset signal when the microcomputer is in an abnormal state where the watchdog clear signal is not generated; the monitoring device is reset by the watchdog clear signal; A watchdog counter is provided that is maintained in a reset state by a reset command from the power supply reset device, and an output signal generated when the watchdog counter overflows is used as a reset command together with a reset signal from the power supply reset device. A microcomputer monitoring and control device, characterized in that the microcomputer is connected by a wired OR and supplied to the microcomputer.