JPH0269940A - Semiconductor integrated circuit bonding pad configuration - Google Patents

Semiconductor integrated circuit bonding pad configuration

Info

Publication number
JPH0269940A
JPH0269940A JP63221924A JP22192488A JPH0269940A JP H0269940 A JPH0269940 A JP H0269940A JP 63221924 A JP63221924 A JP 63221924A JP 22192488 A JP22192488 A JP 22192488A JP H0269940 A JPH0269940 A JP H0269940A
Authority
JP
Japan
Prior art keywords
semiconductor integrated
bonding pad
integrated circuit
bonding
pad configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63221924A
Other languages
Japanese (ja)
Inventor
Tooru Hokari
甫仮　透
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP63221924A priority Critical patent/JPH0269940A/en
Publication of JPH0269940A publication Critical patent/JPH0269940A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路のボンディングパッドの形状に
関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the shape of bonding pads of semiconductor integrated circuits.

〔発明の概要１ 本発明はボンディングパッド表面に凹凸を設け、ボンデ
ィングワイヤーの単位面積当りの接触面積の増大を計る
ことにより、ボンディングパッドとボンディングワイヤ
ーの接触不良を防止するとともに、半導体集積回路の設
計制約条件を緩和し、小型化、及び、コストダウンを実
現したものである。[Summary of the invention 1] The present invention prevents poor contact between the bonding pad and the bonding wire by providing unevenness on the surface of the bonding pad and increasing the contact area per unit area of the bonding wire, and also improves the design of semiconductor integrated circuits. This reduces constraints, reduces size, and reduces costs.

〔従来の技術Ｊ 従来のボンディングパッドの形状は、凹凸を形成せず、
平坦な形状であった。[Conventional technology J The shape of the conventional bonding pad does not form unevenness,
It had a flat shape.

［発明が解決しようとする課題］ しかし、前述の従来技術では、ボンディングの強度はボ
ンディングワイヤーとボンディングパッドの接触面積に
比例するため、ボンディングパッドのサイズを大きくし
なければならない等の問題を有する。[Problems to be Solved by the Invention] However, the above-mentioned conventional technology has problems such as the need to increase the size of the bonding pad because the bonding strength is proportional to the contact area between the bonding wire and the bonding pad.

そこで、本発明はこのような問題点を解決するもので、
その目的とするところは品質の高い小型で低コストの半
導体集積回路、及び、半導体集積回路組立品を提供する
ところにある。Therefore, the present invention aims to solve these problems.
The purpose is to provide high-quality, small, low-cost semiconductor integrated circuits and semiconductor integrated circuit assemblies.

［課題を解決するための手段１ 本発明の半導体集積回路ボンディングパッド形状は、ボ
ンディングパッドの表面に積極的に凹凸を設けることを
特徴とする。[Means for Solving the Problems 1] The semiconductor integrated circuit bonding pad shape of the present invention is characterized by actively providing irregularities on the surface of the bonding pad.

［実　施　例］ 第１図は本発明の１実施例を示す半導体集積回路の断面
図である １はボンディングパッドのメタル配線層、２は半導体集
積回路のコーティング層、３はボンディングパッド部分
のメタル配線層に到るまでの前工程層である。[Embodiment] FIG. 1 is a cross-sectional view of a semiconductor integrated circuit showing one embodiment of the present invention. 1 is a metal wiring layer of a bonding pad, 2 is a coating layer of a semiconductor integrated circuit, and 3 is a metal layer of a bonding pad portion. This is a pre-process layer leading up to the wiring layer.

第２図は本発明を使用した半導体集積回路のボンディン
グの１実施例を示す断面図である。４はボンディングワ
イヤーである。FIG. 2 is a sectional view showing one embodiment of bonding of a semiconductor integrated circuit using the present invention. 4 is a bonding wire.

第１図に示すボンディングパッド部分のメタル配線層ｌ
の凹凸は、メタル配線層１に到るプロセス上の操作、又
は、メタル配線層１に直接プロセス処理を加える等の方
法で設ける。Metal wiring layer l of the bonding pad portion shown in Figure 1
The unevenness is provided by a process operation leading to the metal wiring layer 1 or by directly applying a process treatment to the metal wiring layer 1.

第２図に示す如く、ボンディングワイヤー４とメタル配
線層１の接合面は、メタル配線層ｌの凹凸により拡大さ
れ、平坦な接合面より強度の高いボンディングが得られ
る。またボンディングの接合面が小さくても高い強度が
得られるため、ボンディングパッド自体の開口面積を小
さくでき、ボンディングの接合面の縮小によるボンディ
ング材の消費を軽減するとともに、半導体集積回路の設
計条件が緩和され、デツプの小型化が可能となりコスト
ダウンが計れる。As shown in FIG. 2, the bonding surface between the bonding wire 4 and the metal wiring layer 1 is enlarged by the unevenness of the metal wiring layer 1, and a stronger bonding can be obtained than with a flat bonding surface. In addition, high strength can be obtained even if the bonding surface is small, so the opening area of the bonding pad itself can be reduced, reducing the consumption of bonding material due to the reduction of the bonding surface, and easing the design conditions for semiconductor integrated circuits. As a result, the depth can be made smaller and costs can be reduced.

（発明の効果］ 以上述べたように本発明によれば、ボンディングパッド
の表面に凹凸を形成することにより、半導体集積回路の
ボンディング品質が向上するとともに、ボンディング材
の消費軽減、チップの小型化による低コスト化が達成で
きるという効果を有する。(Effects of the Invention) As described above, according to the present invention, by forming irregularities on the surface of the bonding pad, the bonding quality of semiconductor integrated circuits is improved, the consumption of bonding material is reduced, and the size of the chip is reduced. This has the effect that cost reduction can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の半導体集積回路の一実施例を示す主要
断面図。 第２図は本発明を使用した半導体集積回路のボンディン
グの一実施例を示す主要断面図。 １・・・ボンディングパッド部分のメタル配線層 ２　・ コーティング層 ３・・・ボンディングパッドのメタル配線層に到る前工
程層 ４・・・ボンディングワイヤー 以上 出願人　セイコーエプソン株式会社FIG. 1 is a main sectional view showing an embodiment of a semiconductor integrated circuit according to the present invention. FIG. 2 is a main cross-sectional view showing one embodiment of bonding of a semiconductor integrated circuit using the present invention. 1... Metal wiring layer of the bonding pad portion 2 - Coating layer 3... Pre-process layer leading to the metal wiring layer of the bonding pad 4... Bonding wire and above Applicant: Seiko Epson Corporation

Claims (1)

【特許請求の範囲】[Claims] 半導体集積回路におけるボンディングパッドの表面に凹
凸を設けたことを特徴とする半導体集積回路ボンディン
グパッド形状。A bonding pad shape for a semiconductor integrated circuit characterized in that the surface of the bonding pad in the semiconductor integrated circuit is uneven.
JP63221924A 1988-09-05 1988-09-05 Semiconductor integrated circuit bonding pad configuration Pending JPH0269940A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63221924A JPH0269940A (en) 1988-09-05 1988-09-05 Semiconductor integrated circuit bonding pad configuration

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63221924A JPH0269940A (en) 1988-09-05 1988-09-05 Semiconductor integrated circuit bonding pad configuration

Publications (1)

Publication Number Publication Date
JPH0269940A true JPH0269940A (en) 1990-03-08

Family

ID=16774291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63221924A Pending JPH0269940A (en) 1988-09-05 1988-09-05 Semiconductor integrated circuit bonding pad configuration

Country Status (1)

Country Link
JP (1) JPH0269940A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996037332A1 (en) * 1995-05-26 1996-11-28 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
JP2006213027A (en) * 2005-02-07 2006-08-17 Alps Electric Co Ltd Thermal head and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996037332A1 (en) * 1995-05-26 1996-11-28 Formfactor, Inc. Fabricating interconnects and tips using sacrificial substrates
JP2006213027A (en) * 2005-02-07 2006-08-17 Alps Electric Co Ltd Thermal head and manufacturing method thereof

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