JPH0269975A - Semiconductor memory and manufacture of the same - Google Patents

Abstract

PURPOSE:To obtain a large capacitor area with a small occupation area by laminating a capacitor on a MOSTr through an insulating film and connecting a lower capacitor electrode to a source or drain diffusion layer through a contact hole made in the insulating film. CONSTITUTION:An element separation oxide film 2 is formed on a p type Si substrate 1 and a gate oxide film 3 is formed thereon. Polycrystalline Si film gate electrodes 41 and 42 are formed and impurity ions are implanted to form n type layers 5 and 6. Thereby a MOSTr is obtained. An SiO2 film 7 is deposited and a polycrystalline Si film 8 is deposited on the whole surface. A contact hole 9 is made and a recession 10 is formed. After a polycrystalline Si film 11 is deposited on the whole surface, an n type layer 12 is formed by implanting As and patterned to obtain a lower capacitor electrode. After a capacitor insulating film 13 is formed on the surface of said electrode, a polycrystalline Si film 14 is deposited and patterned to form an upper capacitor electrode. An SiO2 film 15 is deposited, a contact hole is made, and a bit line 16 is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor memory device, and more particularly to the structure and manufacturing method of a dynamic RAM (DRAM) having a stacked capacitor cell structure.

(Prior Art) As DRAMs continue to become more highly integrated, the area of capacitors decreases, causing serious problems such as erroneous reading of memory contents and data destruction due to radiation. In order to solve these problems, proposals have been made to provide capacitors with various structures. One of them is the multilayer capacitor.
It has a cell structure. In this method, a MOS transistor is first formed on an isolated semiconductor substrate, then an insulating film is covered over the MOS transistor, a contact hole is formed in the MOS transistor, and a lower capacitor electrode is formed to contact the source or drain diffusion layer of the MOS transistor. Then, an upper capacitor electrode is formed via a capacitor insulating film to form a memory cell.

In such a stacked capacitor cell structure.

Planarly, without increasing the area occupied by memory cells,
The surface area of the lower capacitor electrode can be increased to ensure a substantial area of the capacitor. However, the conventional stacked capacitor cell structure and manufacturing method have the following problems when achieving higher integration.

First, in order to increase the surface area of the lower capacitor electrode and obtain sufficient capacitance, the film thickness must be at least 3000 mm in order to effectively utilize the side surfaces of the lower capacitor electrode.
We have to connect with the thick thing called people. It is difficult to microfabricate such thick lower capacitor electrodes, which may cause short circuits between the lower capacitor electrodes. Furthermore, if the lower capacitor electrode is thick, the aspect ratio of the bit line contact hole becomes high, causing the bit line to become thin or broken in two stages at the contact hole portion, causing defects.

Furthermore, when the lower capacitor electrode is brought into contact with the source or drain diffusion layer, since the contact area is small, it is necessary to implant impurity ions at a high concentration near the interface in order to achieve good conduction with good yield. Then, this ion-implanted impurity is diffused in the subsequent thermal process, and M
This may deteriorate the characteristics of the OS transistor or cause an increase in leakage current between adjacent cells. This effect is particularly large when phosphorus, which is an n-type impurity, is used.

(Problem to be solved by the invention) As described above, the DR of the conventional stacked capacitor cell structure
With the AM manufacturing method, it is still insufficient to obtain a reliable and sufficient capacitor area.

Another problem is that it is difficult to make good contact at the contact portion of the lower capacitor electrode without impairing device characteristics.

The present invention is a multilayer capacitor that solves these problems.
An object of the present invention is to provide a DRAM with a cell structure and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) A DRAM according to the present invention has a capacitor stacked on a MOS transistor with an insulating film interposed therebetween.

It is based on a stacked capacitor cell structure in which a lower capacitor electrode contacts a source or drain diffusion layer of a MOS transistor through a contact hole formed in an insulating film. In this basic structure, the present invention is configured such that the contact hole penetrates the insulating film and then makes a recess of a predetermined depth from the substrate surface, and a lower capacitor electrode is provided outside the contact hole on the insulating film. It is characterized by having a base conductor film that is patterned at the same time and becomes a part of the lower capacitor electrode.

The method for manufacturing a DRAM of the present invention is to cover a substrate on which MO8+- transistors are formed with a first insulating film, and then, before forming a contact hole thereon, coat a first conductive film that will become a part of a lower capacitor electrode. A contact hole is formed in the laminated film of the first insulating film and the first conductive film. At this time, the substrate surface exposed in the contact hole is further selectively etched to form a recess. Then, a second conductive film is formed, which becomes the remainder of the lower capacitor electrode that contacts the source or drain diffusion layer of the MOS transistor, and becomes part of the source or train diffusion layer by diffusion of impurities from this second conductive film. After forming the diffusion layer, the first and second conductor films are simultaneously patterned to form a lower capacitor electrode. Next, an upper capacitor electrode is formed using a third conductor film with the capacitor insulating film interposed therebetween. Finally, the entire surface is covered with a second insulating film, contact holes are made, and the MOS
A bit line is formed in contact with the drain or source diffusion layer of the transistor.

(effect) In the stacked capacitor cell structure of the present invention.

It is disposed on the base conductor film of the lower capacitor electrode or on the insulating film around the contact portion of the lower capacitor electrode, and a recess is further formed on the substrate surface exposed to the contact hole. Therefore, the surface area of the lower capacitor electrode is very large, resulting in a large cell capacitor capacitance.

In this case, since a recess is formed on the surface of the substrate at the contact hole, a sufficiently large capacitor area can be obtained without making the base conductor film that forms part of the lower capacitor electrode very thick. Therefore, the processing and formation of bit lines and bit line contacts becomes easy.

In addition, in the method of the present invention, a recess is formed in the contact hole of the lower capacitor electrode with the insulating film and the first conductive film laminated, and the second conductive film is deposited to form the source and drain layers by subsequent impurity diffusion. Forms part of the diffusion layer. Therefore, even if the contact hole is small, source the inner surface of the recess.

Since it can be used as a drain diffusion layer, a sufficiently low contact resistance can be obtained. Since this diffusion layer is formed by solid-phase diffusion, re-diffusion caused by subsequent thermal processing can be sufficiently reduced, and deterioration of transistor characteristics and leakage between cells can be significantly reduced.

(Example) Hereinafter, two embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing a DRAM cell structure according to an embodiment of the present invention. Figures 2(a) to (g) are.

DRAM according to the method of one embodiment of the present invention to obtain this structure
It is a sectional view showing a cell manufacturing process. To explain this DRAM cell according to the manufacturing process, as shown in FIG. 2(a), an element isolation oxide film 2 is formed on a p-type silicon substrate 1 by, for example, a selective oxidation method. Next, a gate oxide film 3 is formed by thermal oxidation by about 150 people, and a polycrystalline silicon film is deposited.

A gate electrode 4 (4+, 42) is formed by patterning, and an n-type layer 5.6, which is a source and drain diffusion layer, is formed by ion implantation of impurities. Thereby, a MOS transistor of the memory cell is obtained. The gate electrode 4 is
They are continuously arranged in one direction of the memory cell array and serve as word lines. After that, as shown in FIG. 2(a), a CVD5i02 film (first insulating film) 7, which will become a nine-layer insulating film, is deposited on the entire surface, and then a first conductive film, which will become a part of the lower capacitor electrode, is deposited on the entire surface. The first polycrystalline silicon film 8 is
Approximately 0 people will accumulate.

Thereafter, as shown in FIG. 2(b), the capacitor electrode is
A contact hole 9 for contacting the mold layer 6 is opened, and the exposed substrate surface is further etched to a depth of about 1 μm to form a recess 10 as shown in FIG. 2(C). Then, as shown in FIG. 2(d), a second polycrystalline silicon film 11 with a thickness of approximately 500 mm is deposited as a second conductive film over the entire surface. After depositing this polycrystalline silicon film 11.

Accelerating voltage 9 with a range similar to the film thickness, for example 60k
Arsenic ions are implanted at eV at a dose of 10"/cm2, and by diffusion from this polycrystalline silicon film, an n-type layer 12, which will become part of the source and drain layers, is formed on the inner surface of the recess 10. As shown in FIG. 2(e), the laminated film of the first and second polycrystalline silicon films 8 and 11 is simultaneously patterned to obtain a lower capacitor electrode.

After that, a capacitor insulating film 13 is formed on the surface of the lower capacitor electrode by thermal oxidation, and then a third conductor film is formed as a third conductive film.
A polycrystalline silicon film 14 is deposited and patterned to form an upper capacitor electrode.

Thereafter, as shown in FIG. 2(g), a CVD5i02 film (second insulating film) 15 was deposited as an interlayer insulating film over the entire surface, and contact holes were formed in this.

The bit line 16 is disposed using a molybdenum silicide film, A, & film, etc. to complete the process.

In this embodiment, a base conductor film is provided around the contact portion of the lower capacitor electrode of the multilayer capacitor,
Moreover, since a recess is formed in the substrate surface of the contact hole, a very large capacitor area can be obtained. In other words, the cell capacity can be increased without increasing the thickness of the underlying conductor film, and DRAM
can be highly reliable.

Further, according to this embodiment, by forming the recess 10 in the exposed surface of the substrate in the contact hole 9, the contact resistance between the lower upper capacitor electrode and the substrate can be made sufficiently small. In particular, the diffusion layer formed on the inner surface of this recess is caused by solid-phase diffusion from the polycrystalline silicon film that becomes the lower capacitor electrode, and the junction depth and concentration can be controlled to be sufficiently shallow, thereby preventing deterioration of transistor characteristics. It is possible to prevent an increase in leakage between cells. As described above, according to this embodiment, a highly reliable DRAM can be obtained.

[Effects of the Invention] As described above, according to the present invention, the thickness of the lower capacitor electrode does not have to be increased so much.

A large capacitor area can be obtained with a small footprint and therefore also. A DRAM with a stacked capacitor structure that achieves high reliability without inter-cell leakage etc. can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a DRAM structure according to an embodiment of the present invention, and FIGS. 2(a) to 2(g) are sectional views showing the memory cell manufacturing process thereof. 1...p-type silicon substrate, 2...element isolation oxide film,
3... Gate insulating film, 4... Gate electrode, 5°6.
...n-type layer (source, drain diffusion layer), 7...CV
DSiO2 film (first insulating film), 8--first conductor film (first polycrystalline silicon film), 9--contact hole,
10... Concave portion, 11... Second conductor film (second polycrystalline silicon film), 13... Capacitor insulating film. 14...Third conductor film (third polycrystalline silicon film) 1
5-CVD5 i 02 film (second insulating film), 16...
・Bit line. Applicant's agent Patent attorney Takehiko Suzue

Claims (3)

[Claims] (1) A MOS transistor formed on a semiconductor substrate,
A memory cell is constructed of a capacitor stacked on a substrate on which this MOS transistor is formed via an insulating film, and a lower capacitor electrode contacts the source or drain diffusion layer of the MOS transistor through a contact hole formed in the insulating film. In the semiconductor memory device, the contact hole is configured to penetrate the insulating film and then make a recessed portion of a predetermined depth from the substrate surface, and a pattern is formed on the outside of the contact hole on the insulating film at the same time as a lower capacitor electrode. What is claimed is: 1. A semiconductor memory device comprising a base conductor film which is formed into a base conductor film and becomes a part of a lower capacitor electrode. (2) A method for manufacturing a semiconductor memory device in which a memory cell is configured by a MOS transistor and a capacitor, which includes a step of forming a MOS transistor on a semiconductor substrate on which an element isolation region is formed, and a step of forming a MOS transistor on the substrate on which the MOS transistor is formed. A process of covering with a first insulating film and then laminating a first conductive film that will become a part of the lower capacitor electrode, and forming a contact hole in the laminated film of the first insulating film and the first conductive film. Then, the substrate surface exposed in the contact hole is etched to form a recess, and a second conductor film is deposited to contact the source or drain diffusion layer of the MOS transistor and become the remainder of the lower capacitor electrode. a step of forming a diffusion layer to become a part of a source or drain diffusion layer on the inner surface of the recess by diffusion of impurities from a second conductor film; and a step of simultaneously patterning the first and second conductor films to form a lower capacitor electrode. forming an upper capacitor electrode made of a third conductive film on the surface of the formed lower capacitor electrode via a capacitor insulating film; and forming a second insulating film on the substrate on which the upper capacitor electrode is formed. Cover it with a film and make a contact hole in it to create a MOS
1. A method of manufacturing a semiconductor memory device, comprising the step of forming a bit line in contact with a drain or source diffusion layer of a transistor. (3) A method for manufacturing a semiconductor memory device in which a memory cell is configured by a MOS transistor and a capacitor, which includes a step of forming a MOS transistor on a semiconductor substrate on which an element isolation region is formed, and a step of forming a MOS transistor on the substrate on which the MOS transistor is formed. A step of covering with a first insulating film and then layering a first polycrystalline silicon film that will become a part of the lower capacitor electrode, and a step of forming a laminated film of the first insulating film and the first polycrystalline silicon film. A step of forming a contact hole and etching the surface of the substrate exposed in the contact hole to form a recess, and forming a second polycrystalline silicon layer that contacts the source or drain diffusion layer of the MOS transistor and becomes the remainder of the lower capacitor electrode. A process of depositing a film, and implanting impurity ions into the second polycrystalline silicon film using an acceleration voltage having a range comparable to the thickness of the second polycrystalline silicon film, and by diffusing the impurity from the second polycrystalline silicon film, a step of forming a diffusion layer to become a part of a source or drain diffusion layer on the inner surface of the recess; a step of simultaneously patterning the first and second polycrystalline silicon films to form a lower capacitor electrode; A step of forming an upper capacitor electrode made of a third polycrystalline silicon film on the surface of the lower capacitor electrode via a capacitor insulating film, and covering the substrate on which the upper capacitor electrode is formed with a second insulating film and contacting this. 1. A method of manufacturing a semiconductor memory device, comprising the step of forming a bit line in contact with a drain or source diffusion layer of a MOS transistor by forming a hole.