JPH0271175A - Method for troubleshooting logical circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a fault diagnosis method for logic circuits that employs a scan path method.

[Conventional technology]

Conventionally, this type of fault diagnosis method uses a fault dictionary (for example, the method described by Kenji Kani et al.
Fundamentals of D, 1 Omisha, 1983).

In the method using a fault dictionary, a fault is assumed in the circuit, a fault simulation is performed in advance using a test pattern that detects the fault, and a synbutton for the assumed fault is created and maintained for each test pattern. The suspected target failure is estimated by comparing the test results.

[Problem to be solved by the invention]

The conventional Fault II method described above uses fault simulation to find symptoms, so as the circuit scale increases, the number of hypothetical faults also increases, and the number of required test patterns also increases, so the calculation time required for fault simulation increases exponentially. The disadvantage is that it increases.

[Means to solve the problem]

The logic circuit fault diagnosis method of the present invention includes a fault definition means for defining all faults in the circuit as simulation target faults for a logic circuit simulation model employing a scan path method, and a tester for the simulation target faults. fault simulation means for performing a fault simulation on the test pattern determined to be an error, and detecting a fault detectable at the observation point determined as an error as a suspect fault; a set calculation means for selecting faults that are detected repeatedly; a repetition count means for counting the number of times the faults selected by the set calculation means have been duplicated; It has a suspected target fault output means for estimating a target fault, and a suspected target fault output means for outputting the estimated suspected target fault.

[Effect]

Since a fault simulation is performed for a pattern determined to be an error by the tester and a suspected fault is detected, the time required for fault simulation does not increase significantly even if the circuit scale increases. In addition, since the suspected fault is estimated based on the number of repeated detections of faults, the suspected fault can be sufficiently estimated even when there are multiple faults detected in the pattern test circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a 70-chart of an embodiment of the fault diagnosis method for a logic circuit according to the present invention.

The fault diagnosis method of this embodiment is comprised of a fault definition means 1, a fault simulation means 2, a set calculation means 3, a repetition count means 4, a suspected target fault estimation means 5, and a suspected target fault output means 6.

First, the fault definition means 1 inputs the simulation model 102 of the circuit under test 101, defines all the faults in the circuit, and outputs the fault 7 to be simulated.

Next, the fault simulation means 2 executes the circuit under test 10.
1 and the test pattern 103 as inputs, the error output test pattern 105 determined to be an error by the tester 104, the simulation model 102, and the simulation target fault 7 which is the output of the fault definition means 1 are input, and the error output test pattern is generated. 105 outputs a detectable fault 8. Subsequently, the set calculation means 3 uses the detectable faults 8 determined by the fault simulation means 2 as input to select redundantly detected faults and non-redundant faults.

At this time, for faults that are detected repeatedly, the number of times the faults are detected is counted by the number of times counting means 4.

From the results of the set calculation means 3 and the repetition count means 4,
The suspected target fault estimating means 5 estimates the suspected target fault based on the redundantly detected fault and the number of duplications. Finally, the results obtained by the suspected target fault estimation means 5 are displayed on the list display 9 by the suspected target fault output means 6.

FIG. 2 shows a fault simulation means 2, a set calculation means 3, a repetition count means 4, and a suspected target fault estimation means 5.
2 is a flowchart showing details of the process.

For the fault detected by the fault simulation means 2,
The process of checking whether there are duplicate faults and estimating the fault that is the suspect fault is shown below.

Here, step 11 corresponds to the failure simulation means 2, step 13. Step 16゜Step 18.
Step 20. Step 21. Step 23 corresponds to the set calculation means 3. Step 14. Step 17. Step 19. Steps 22 and 24 correspond to the repeat count counting means 4. Further, step 26 corresponds to the suspected target fault estimation means 5.

First, tester 1
Error output test pattern 1 that was determined to be an error in 04
05 to perform a fault simulation and find a detectable fault 8 (step 11). At this time, tester 104
In step 12), it is determined whether there is only one pattern determined as an error in step 12), and if there is only one, the detectable fault 8 obtained by the fault simulation is determined as a non-duplicate detected fault in step 13). The number of times is set to O (step 14). If not, it is determined whether it is the first pattern (step 15), and if it is the first pattern, the fault found in the first fault simulation is determined as a non-duplicate detection fault (step 16), and ffi is set as the number of times (step 17). For the second and subsequent patterns, check whether there are duplicate failures (
Step 18). At this time, if there is an element that overlaps with an element of the set of duplicate detected failures, the number of duplicates for that failure is counted up (step 19). Roughly, it is checked whether it overlaps with the elements of the set of non-overlapping detected faults (step 20). At this time, if there is a duplicate fault, that fault is added to the set of duplicate detected faults and deleted from the non-duplicate detected fault set (step 21), and the number of duplicates is set to 1 (step 22). In addition, if there is no overlapping fault in step 20, the detected fault is set as a non-overlapping detected fault and step 23
), and the number of repetitions is set to 0 (step 24). tester 10
Determine whether the duplication check has been completed for all the patterns judged as errors in step 4 (step 25). Once completed, check the set of duplication detected faults, and the faults that have a large number of duplications have a high proportion of suspect faults. It is estimated that (
Step 26).

FIG. 3 is a diagram showing an example of a logic circuit targeted by the fault diagnosis method of this embodiment.

Table 1 shows a test pattern, an output reading value, and an output result of the circuit under test when the logic circuit of FIG. 3 is tested with the tester 104 as the circuit under test 101.

Table 2 is a table showing detectable faults 8 obtained by executing the fault simulation means 2 based on the results of Table 1.

In this table, for example, a stuck-at-1 fault of B is expressed as 8/1.

Table 3 shows the set calculation means 3 based on the detectable faults shown in Table 2.
This is a table showing duplication detection failures and non-duplication detection failures obtained by the duplication frequency counting means 4.

The number in parentheses is the number of duplicates.

Table 2 In Table Process 1, the faults that can be detected at the observation point on the Y side of pattern number 1 are treated as non-overlapping detected faults. In process 2, the fault that can be detected at the observation point on the X side of pattern number 3 and the process 1
From the result, the 8/1 and 1/1 faults are detected redundantly, so these two faults are treated as redundantly detected faults and the number of overlaps is set to 1, and the other faults are treated as non-duplicately detected faults. . In process 3, based on the faults that can be detected at the observation point on the X side of pattern number 5 and the results of process 2, the number of duplicates of 8/1 and L/1 for duplicate detection failures is set to 2, and then B
The 1/1 and X/1 faults are newly added to the overlap detection faults with the number of overlaps being 1, and the other faults are set as non-overlap detection faults. In step 4, based on the faults that can be detected at the observation point on the Y side of pattern number 5 and the results of step 3 above, all faults that were treated as non-duplicate detection faults are treated as duplicate detection faults with a duplication count of 1, and are replaced by duplicate detection. For each failure treated as a failure, the number of duplications is increased by one. Finally, the suspected target fault means 5 estimates that the 1 stuck-at fault of B and the 1 stuck-at fault of L are highly suspected to be the suspected target faults from Table 3.

〔Effect of the invention〕

As explained above, the present invention focuses on a pattern that causes an error in a tester, performs a fault simulation, and estimates a suspected fault, thereby reducing the computational cost compared to a fault dictionary creation method in which a fault dictionary is created in advance. This can be a significant resource saver and, in many cases,
It is rare for a fault to be detected in only one pattern, and if we follow the premise that it is normally detected in multiple patterns, we can estimate the suspected fault for the pattern that caused the tester error. By this,
This has the effect of preventing erroneous diagnosis such as overlooking the true fault during estimation.Furthermore, when estimating a suspected fault, the faults that are detected repeatedly and the number of times they overlap are It also has the effect of providing a measure of the strength of the fault, and the ability to sufficiently estimate the suspected fault even when multiple faults overlap in the circuit under test.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing an embodiment of the logic circuit fault diagnosis method of the present invention, and FIG. 2 shows the fault simulation means 2, set calculation means 3, repetition count means 4, and suspected target fault estimation means of FIG. FIG. 3 is a flowchart showing the details of step 5, and FIG. 3 is a diagram showing an example of a logic circuit targeted by the fault diagnosis method of this embodiment. 101... Circuit under test 102... Simulation model 103... Test pattern 104... Tester 105... Error output test pattern... Fault definition means 2... Fault simulation means 3...・Set calculation means 4...duplication frequency counting means 5...suspect target fault estimation means 6...suspect target fault display means 7...simulation target fault 8...detectable fault 9...list display Patent applicant Nippon Kata Kei Co., Ltd. Company agent
Patent Attorney Uchihara Oto Mazu

Claims (1)

[Claims] 1. For a simulation model of a logic circuit that employs a scan path method, a fault definition means for defining all faults in the circuit as faults to be simulated, and a tester determining the faults to be simulated as errors. a fault simulation means that performs a fault simulation on the detected test pattern and detects as a suspect fault a fault that can be detected at an observation point determined to be an error; a set calculation means for sorting detected faults; a duplication count means for counting the number of duplicate detections of the faults selected by the set calculation means; A fault diagnosis method for a logic circuit, comprising a suspected target fault estimation means for estimating a target fault, and a suspected target fault output means for outputting the estimated suspected target fault.