JPH0272072U

JPH0272072U -

Info

Publication number: JPH0272072U
Application number: JP15162088U
Authority: JP
Priority date: 1988-11-21
Filing date: 1988-11-21
Publication date: 1990-06-01
Anticipated expiration: 2003-11-21
Also published as: JPH0628854Y2

Description

[Brief explanation of the drawing]

第１図は本考案を実施した垂直偏向回路の回路
図であり、第２図はその各部の信号波形図である
。第３図は従来例のブロツク図である。ＴＲ_１……第１トランジスタ、ＴＲ_２……第２
トランジスタ、ＴＲ_３……第３トランジスタ、Ｔ
Ｒ_４……第４トランジスタ、１……垂直偏向コイ
ル、３，４……時定数回路。 FIG. 1 is a circuit diagram of a vertical deflection circuit embodying the present invention, and FIG. 2 is a signal waveform diagram of each part thereof. FIG. 3 is a block diagram of a conventional example. _TR1 ...first transistor, _TR2 ...second
Transistor, TR ₃ ...Third transistor, T
R ₄ ... Fourth transistor, 1... Vertical deflection coil, 3, 4... Time constant circuit.

Claims

[Scope of utility model registration request]

differentially connected first and second transistors that switch the direction of current flowing through the load;
A differentially connected third and fourth transistor constituting a current source of the transistor, and a first half and a second half of the sawtooth wave current flowing to the load, which is connected to the control electrodes of each of the third and fourth transistors. a time constant circuit that controls the third and fourth transistors so that a sawtooth wave current flows through the third and fourth transistors; a set of the first and fourth transistors; and a set of the first and fourth transistors;
, means for determining the cycle at which the third set of transistors alternately turns on and off;