JPH0272636A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable only hetero junction to be selectively disordered by making the impurity concentration of a third III-V compound semiconductor layer thicker than those of first and second III-V compound semiconductor layers, and forming a disordered layer selectively by heat treatment. CONSTITUTION:A first III-V compound semiconductor layer 2, a second III-V compound semiconductor layer 3, and a fourth III-V compound semiconductor layer 4 being different in forbidden band width from the second III-V compound semiconductor layer 3 are formed in order on a semiconductor substrate 1. And the impurity concentration of the third III-V compound semiconductor layer 4 where an ohmic region is formed is made thicker than those of the first and second III-V compound semiconductor layers 2 and 3, and those are heat-treated. In this heat treatment, Si diffuses from the third III-V compound semiconductor layer 4 into the second III-V compound semiconductor layer 3, and following this a disordered region 6 is formed. Hereby, only the ohmic region having hetero junction can be diordered selectively without disordering the channel part.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device having a petrojunction, and more particularly to the structure and manufacturing method of a field effect transistor with low parasitic resistance.

[Conventional technology]

In recent years, A fl Ga As / Ga As
In system superlattices, Japanese Journal of Applied Physics, 11 (1985) pp. 1498-1502 (Jpn, J. Appl.
Vol.

24, Crow 11. As discussed in ρp1498-1502), it is known that impurity ion implantation causes interdiffusion of AQ and Ga, resulting in disorder.

[Problem to be solved by the invention]

In the above conventional technology, since ion implantation causes disorder, it is difficult to form a shallow n-type region when applied to a field effect transistor, for example, and a channel is difficult to form during heat treatment for activating implanted ions. There was a problem in that impurities in the area also diffused, making it difficult to control the threshold value.

An object of the present invention is to selectively disorder only an ohmic region having a Peter junction in an electronic device, particularly a field effect transistor, without disordering the channel portion.

[Means to solve the problem]

The above object is to provide a first group III-V raw conductor layer having an active layer formed on a semiconductor substrate, and a second group III-V semiconductor layer formed on the first group III-V semiconductor layer. and the second ■- selectively formed on the second m-V group semiconductor layer.
In a semiconductor device having a third m-V group semiconductor layer having a different forbidden band width from that of the v-group semiconductor layer, the impurity concentration of the third m-V group semiconductor layer in the row forming the ohmic region is set to This can be achieved by making the impurity concentration higher than that of the m-V group semiconductor layer in No. 2 and by heat treatment. For example, S
i-doped G a As / A Q G a As
In a field effect transistor having a heterostructure,
This can be achieved by increasing the Si concentration of the S1-doped GaAs layer forming the ohmic region compared to the Si concentration of the channel portion and by performing heat treatment.

[Effect]

The present invention will be explained in detail with reference to FIGS. 1(a) to 1(c). Undoped GaAs 2 is formed on the GaAs substrate 1 using a molecular beam epitaxy (MBE) method or a metal organic vapor phase component (MOCVD) method.

Al2GaAs3. Si-topped GaAs4 is sequentially grown epitaxially (FIG. 1(a)). Next, Figure 1(b)
Then, selectively 4Si-doped G was formed by dry etching.
After removing the a As 4, the Si○2 film 5 is increased in thickness. Next, moving to FIG. 1(c), when heat treatment is performed, Si from S1-doped GaAs4 diffuses into Al20aAs3, and a disordered region 6 is formed accordingly. Figure 2 shows Si-doped Ga after heat treatment at 700'C for 3 hours.
The Si concentration of the As layer 4 and the thickness of the disordered region 6 are shown.

5X10111cm- in S1-doped G a As layer 4
When 3AQGaAsJW is doped with 2×10"l1cm-3Si, the thickness of 6 is about 50 nm, but 3
Since the Si concentration is low at the interface between and 2, disorder hardly occurs. This achieves selective disordering of only 6. This takes advantage of the increase in disorder associated with an increase in Si concentration, and selectively disorder only the heterointerface in the heavily doped region, resulting in contact due to band discontinuity ΔEc at the Peter interface. Resistance ρ. This is to reduce the

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Example 1 Example 1 of the present invention will be described using FIGS. 3(a) to 3(d). As shown in Figure 3(a), semi-insulating GaA
Undoped GaAs layer 12 (thickness 500 nm), undoped AQ, 3G a
o, , As layer 13 (thickness 6 nm), Si-doped AQG
aAs layer 14 (thickness 35 nm, Si concentration 2.4
10"cm-"), undoped A Q03G a
o7A s layer 15 (thickness 10 nm), Si-doped n
-GaAsN! Sequentially epitaxially grow J16 (thickness: 160 nm, Si concentration: 5 x 10" cm-3). Next, deposit Si○2 film 17 (thickness: 720 nm) by vapor phase epitaxy (CVD method), and then form a gate electrode. A photomask 18 for recess etching is formed.Next, moving to FIG. 3(b), the 5102 film 17 is coated with CF4
The system was removed by reactive ion etching (RIE), followed by CCU2F and RIE using gas.
-Remove the GaAs layer 16.

Subsequently, after completely removing the photomask 18 and the 5in 217, a SiO2 film 19 (20 nm) is deposited again by the CVD method. Next, moving to FIG. 3(C), S i O
After protecting the crystal surface with two films 19, it was heated for 70 minutes in an H2 gas flow.
Heat treatment is performed at 0'C for 13 hours.

If heat treatment is performed at a high temperature higher than 700° C., it may take less than one hour, but in order to protect the channel portion, heat treatment at a lower temperature is preferable.

When performing the process at a high temperature of 800° C. or higher, it is preferable to use a so-called rabbit thermal annealing method using lamp heating. Through the above heat treatment, a disordered layer 20 is formed by Si diffusion from the nGaAs layer 16, and the n-
GaAsllG and undoped AQ0.3Gao, tAs
The heterointerface between layers 15 is disordered. Naon-G
a When the A s layer 16 is doped with 81 of 8×101"cm-", undoped A Qo3G a,7A s 1
The heterointerface between 3 and undoped G a A s12 can also be disordered. Next, moving to FIG. 3(d), photolithography is used to deposit and lift off AuGe composite electrodes that will become the source/train electrodes 100, 1.
00'' is formed.Furthermore, Au is evaporated and lifted off as a gate electrode material to form a gate electrode 101, and the field effect transistor is completed.In this FET structure, n
-GaAs layer 16 and undoped A Qn3G ao,
The contact resistance between the 7A 5 layers 15 was about 1/10 of that without heat treatment.

Example 2 Example 2 of the present invention will be described using (a) to FIG. 4(d). As shown in FIG. 4(a), semi-MID G a A
Be-doped Ga is deposited on the s-substrate 21 by the MBE method.
As layer 22 (thickness 500 nm, Be concentration 3X101B
cm-3), Si-doped GaAs layer 23 (thickness 35 nm, Si concentration 1.5 x 10" cm-3), undoped AQo, 3G ao7A s layer 24 (thickness 15
nm), undoped GaAs layer 25 (thickness 5 nm)
), Si-doped AQ, , Gao7As layer 26 (thickness 5
nm, Si concentration 3.5 x 1018c m-3),
Si-doped GaAs layer 27 (thickness 5 nm, Si
(concentration 5 x 101' cm-3) were sequentially laminated. At this time, Si atomic layer doping 30 is applied to the lower portion of the Si-doped GaAs layer 27. Doping level shall be equivalent).

Furthermore, an 8102 film 28 (thickness 200 nm) is added to the crystal surface.
, and a photomask 29 for recess etching.

Next, moving to FIG. 4(b), the SiO2 film 28 is removed by CF4-based RIE, and then Si-doped GaAsN27', 30
remove.

Furthermore, by immersing in Jloo, Si-doped A
Q, 3G ao, , A s , i126 and photomask 29 are removed.

Next, moving to Fig. 4(c), after removing 5in228,
A 5102 film 31 (thickness: 200 nm) is deposited again on the entire surface. Further, the entire sample is heat treated in the same manner as shown in Example 1 to form a disordered layer 32. Although a disordered layer can be formed without using atomic layer doping, atomic layer doping allows disordering at a relatively low temperature.

Next, moving to FIG. 4(d), a field effect transistor is completed by forming source/drain electrodes 33, 33' and gate electrode 34 in exactly the same steps as in Example 1.

In this FET, by disordering the hetero interfaces between layers 27 and 26, between layers 26 and 24, between layers 25 and 24, and between layers 24 and 23, the contact resistance formed by these hetero interfaces is reduced. 1/10 compared to a structure that is not disordered.
It became the following.

〔Effect of the invention〕

According to the invention, for example 2DEG (Ttyo-D
mentional E 1ectron Gas as
(abbreviation) FET and HIG FET (Heter
After crystal growth, a disordered region can be formed only in a predetermined region at a low temperature of 700'C or less, which reduces the contact resistance at the hetero interface and reduces the variation between wafers. It is possible to form a disordered layer with high throughput.

Furthermore, by controlling the annealing temperature and Si concentration, the diffusion distance of Si can be easily controlled, which has the effect of suppressing short channel effects in field effect transistors.

[Brief explanation of the drawing]

1(a) to 1(c) are cross-sectional views for explaining the present invention in detail, FIG. 2 is a diagram showing the relationship between Si concentration and disordered layer thickness, and FIG. a) to FIG. 3(d) are cross-sectional views of the first embodiment of the present invention, and FIG. 4(a) to FIG.
d) is a sectional view of a second embodiment of the invention. Explanation of symbols 1. Substrate, 2. Undoped GaAs layer. 3- AQ GaAs layer, 4- Si-doped GaAs1li, 5-8iO2 film, 6... Disordered layer, 11... Semi-insulating GaAs substrate, 12... Undoped GaAs Layer, 13...An1Cup A Q
o3G ao7A s M, 14-Si doped AQ
GaAsJI? , 15・Undoped AQo3Ga, 7A
s layer, 16-Si doped Ga As Ji, 1
7.19-8i○2 film, 18・Photomask, 20・Disordered layer, 100.100′・Source/drain electrode, 101・Gate electrode, 21・Semi-insulating GaAs
Group 23-Si-doped GaAs layer, 24 =-
Undoped AQo3Gao7As layer, 25・Undoped GaAs layer, 26-8i)'-P A +203Ga(1,7A s
, Ii, 27 .-S i doped Ga As layer,
28.31・5in2 membrane, 29・・Photomask, 30・
...Atomic layer doping region, 32...Disordered layer, 3
3.33'...source/drain electrode, 34 gate electrode.

Claims (1)

[Claims] 1. A semiconductor substrate, a first III-V semiconductor layer having an active layer formed on the semiconductor substrate, and a first III-V semiconductor layer having an active layer formed on the semiconductor substrate.
A second III-V group semiconductor layer formed on a group semiconductor layer and a second III-V group semiconductor layer selectively formed on the second group III-V semiconductor layer are prohibited. A semiconductor device having a disordered layer formed at an interface between a third III-V semiconductor layer having different band widths and forming an ohmic region, and the second and third III-V semiconductor layers. 3's
The impurity concentration of the III-V group semiconductor layer is
A semiconductor device characterized in that the impurity concentration is higher than that of the III-V group semiconductor layer, and the disordered layer is selectively formed by heat treatment. 2. The semiconductor device according to claim 1, wherein an atomic layer doped region is provided at the third III-V group semiconductor layer or at the interface between the second and third III-V group semiconductor layers. 3. The second III-V group semiconductor layer is made of AlGaAs, the third III-V group semiconductor layer is made of GaAs, and the impurity added is Si. The semiconductor device according to item 2. 4. The semiconductor device according to claim 3, wherein the concentration of Si added to the third group III-V semiconductor layer is 5×10^1^8 cm^-^3 or more.