JPH0275210A - Manufacture of thin film resonator - Google Patents

Manufacture of thin film resonator

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Publication number
JPH0275210A
JPH0275210A JP22715488A JP22715488A JPH0275210A JP H0275210 A JPH0275210 A JP H0275210A JP 22715488 A JP22715488 A JP 22715488A JP 22715488 A JP22715488 A JP 22715488A JP H0275210 A JPH0275210 A JP H0275210A
Authority
JP
Japan
Prior art keywords
thin film
layer
film resonator
sio
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP22715488A
Other languages
Japanese (ja)
Other versions
JP2657530B2 (en
Inventor
Hiroshi Ohashi
寛 大橋
Yoshihiko Takeuchi
嘉彦 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Japan Radio Co Ltd
Original Assignee
Japan Radio Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Japan Radio Co Ltd filed Critical Japan Radio Co Ltd
Priority to JP63227154A priority Critical patent/JP2657530B2/en
Publication of JPH0275210A publication Critical patent/JPH0275210A/en
Application granted granted Critical
Publication of JP2657530B2 publication Critical patent/JP2657530B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は薄膜共振部の内部歪応力を分散する構造を有す
る薄膜共振子の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a thin film resonator having a structure that disperses internal strain stress in a thin film resonator.

(従来の技術) 従来のこの種の素子を図面により説明する。(Conventional technology) A conventional element of this type will be explained with reference to the drawings.

第3図は従来のこの種の薄膜共振子の断面図である。同
図において11はシリコン基板、12はエピタキシャル
層、13はSiO□層、14は下部電極、15は圧電体
で、例えばZn0 、16は上部電極である。この種の
素子の動作原理は、下部電極14及び上部電極16に高
周波信号を加えることにより、圧電体15は高周波信号
の周期で伸縮を繰り返し、薄膜共振部、即ちエピタキシ
ャル層12、SiO□層13及び圧電体15の厚さによ
り共振する。
FIG. 3 is a sectional view of a conventional thin film resonator of this type. In the figure, 11 is a silicon substrate, 12 is an epitaxial layer, 13 is a SiO□ layer, 14 is a lower electrode, 15 is a piezoelectric material, for example Zn0, and 16 is an upper electrode. The operating principle of this type of element is that by applying a high frequency signal to the lower electrode 14 and the upper electrode 16, the piezoelectric body 15 repeats expansion and contraction at the period of the high frequency signal, and the thin film resonant portion, that is, the epitaxial layer 12, the SiO□ layer 13, and the thickness of the piezoelectric body 15 causes resonance.

この種の素子の製造方法は、ボロン等を高濃度にドープ
したエピタキシャル層12を(100)シリコン基板上
に形成し、基板裏面を部分的にマスクした後、異方性エ
ツチング液にて基板裏面よりエツチングを行う。エツチ
ングはエビタキシャル層12にて止める。次にSiO□
層13全13ッタリング等で形成し、下部電極14を真
空蒸着法及びフォトリソグラフィ技術により形成する。
The manufacturing method for this type of device involves forming an epitaxial layer 12 doped with boron or the like at a high concentration on a (100) silicon substrate, partially masking the back surface of the substrate, and then etching the back surface of the substrate with an anisotropic etching solution. Perform more etching. Etching is stopped at the epitaxial layer 12. Next, SiO□
The entire layer 13 is formed by uttering or the like, and the lower electrode 14 is formed by vacuum evaporation and photolithography.

圧電体15はスパッタリング等で形成し、上部電極16
を下部電極14同様形成することにより製造する。
The piezoelectric body 15 is formed by sputtering or the like, and the upper electrode 16
It is manufactured by forming the lower electrode 14 in the same manner as the lower electrode 14.

第4図はこの種の素子の他の例の断面図である。FIG. 4 is a sectional view of another example of this type of element.

図面において21はシリコン基板、23ば下部SiO□
層、24は下部電極、25は圧電体、26は上部電極、
27ば上部SiO□層、28は開口部、29は薄膜共振
部保持部である。動作原理は、第3図同様、下部電極2
4及び」二部電極26に加えられた高周波信号により、
圧電体25は伸縮を繰り返し、薄膜共振部、即ち下部S
iO2層23、圧電体25、及び上部SiO□層27の
厚さにより共振する。
In the drawing, 21 is a silicon substrate, 23 is a lower SiO□
layer, 24 is a lower electrode, 25 is a piezoelectric material, 26 is an upper electrode,
27 is an upper SiO□ layer, 28 is an opening, and 29 is a thin film resonator holding portion. The operating principle is the same as in Fig. 3, where the lower electrode 2
The high frequency signal applied to the two-part electrode 26 causes
The piezoelectric body 25 repeatedly expands and contracts, and the thin film resonance part, that is, the lower part S
Resonance occurs due to the thicknesses of the iO2 layer 23, the piezoelectric body 25, and the upper SiO□ layer 27.

次に第4図の構造の製造方法は、開口部28をもつマス
クにより、シリコン基板21上に下部SiO□層23、
下部電極24、圧電体25、上部電極26及び5iO7
を第3図同様の方法にて形成する。
Next, the manufacturing method of the structure shown in FIG.
Lower electrode 24, piezoelectric body 25, upper electrode 26 and 5iO7
is formed by a method similar to that shown in FIG.

次にマスクの開口部28より異方性エツチングし素子を
製造する。
Next, the device is manufactured by anisotropic etching through the opening 28 of the mask.

ここで、上記製造方法において一般に多層に薄膜を形成
する場合、例えば、スパッタリング法にて形成する場合
では基板温度は約600°Cになり、これを室温(約2
5℃)に戻すと熱膨張差のため薄膜界面には歪応力が発
生する。第3図の構造では薄膜共振部は厚み方向に非対
称であり、また第4図の構造では薄膜共振部は厚み方向
に対称であるが、薄膜共振部保持部29では非対称であ
る。
Here, when forming a multilayer thin film in the above manufacturing method, for example, when forming a thin film by sputtering, the substrate temperature is about 600°C, which is lowered to room temperature (about 2°C).
When the temperature is returned to 5° C.), strain stress occurs at the thin film interface due to the difference in thermal expansion. In the structure shown in FIG. 3, the thin film resonant part is asymmetrical in the thickness direction, and in the structure shown in FIG.

このように、第3図、第4図のように従来の薄膜共振子
ではいずれも厚み方向に非対称な部分がある。厚み方向
に非対称であると膜界面の歪応力が多層膜全体として打
ち消さず破壊しやすい欠点があった。
In this way, as shown in FIGS. 3 and 4, conventional thin film resonators all have asymmetrical portions in the thickness direction. If the film is asymmetrical in the thickness direction, the strain stress at the film interface cannot be canceled out by the multilayer film as a whole, resulting in a disadvantage that it is likely to break.

(発明が解決しようとする課題) 上記した薄膜共振子は、素子作製時に蓄積する内部応力
により、薄膜共振部にたわみ、クラックの発生を充分低
減させることは難しかった。
(Problems to be Solved by the Invention) In the above-mentioned thin film resonator, it has been difficult to sufficiently reduce the occurrence of cracks caused by deflection in the thin film resonator portion due to internal stress accumulated during device fabrication.

本発明は、上記問題点を解決するため、薄膜共振部の歪
応力を分散させ、たわみ、クラックの発生を低減させる
構造の薄膜共振子を提供するものである。
In order to solve the above-mentioned problems, the present invention provides a thin film resonator having a structure that disperses the strain stress in the thin film resonator and reduces the occurrence of deflection and cracks.

(課題を解決するための手段) 上記問題点を解決するためになされた本発明の薄膜共振
子の実施例を第1図により詳細に説明する。31はシリ
コン基板、32は保持用5i02層、33は下部SiO
2層、34は下部電極、35は圧電体、36は上部電極
、37は上部5iO7層、39は薄膜共振部保持部、4
0は薄膜共振部とシリコン基板を分離する空間層である
。ここで、圧電体35はZnOに限る必要はな(、A7
+N等でも良い。
(Means for Solving the Problems) An embodiment of the thin film resonator of the present invention, which was made to solve the above problems, will be described in detail with reference to FIG. 31 is a silicon substrate, 32 is a 5i02 layer for holding, and 33 is a lower SiO
2 layers, 34 is a lower electrode, 35 is a piezoelectric body, 36 is an upper electrode, 37 is an upper 5iO7 layer, 39 is a thin film resonator holding part, 4
0 is a space layer separating the thin film resonator and the silicon substrate. Here, the piezoelectric body 35 does not need to be limited to ZnO (A7
+N etc. may also be used.

本発明の素子を動作させるためには、下部電極34と上
部電極36の間に高周波信号を加えることにより、圧電
体35は高周波信号の周期で伸縮を繰り返し、薄膜共振
部、即ち下部SiO2層33、圧電体35及び上部5i
O)4層37の厚さにより共振する。
In order to operate the device of the present invention, by applying a high frequency signal between the lower electrode 34 and the upper electrode 36, the piezoelectric body 35 repeatedly expands and contracts with the period of the high frequency signal, and the thin film resonant portion, that is, the lower SiO2 layer 36 , piezoelectric body 35 and upper part 5i
O) Resonance occurs due to the thickness of the 4th layer 37.

(実施例) 本発明の製造方法を第2図にて説明する。シリコン基板
31表面にスパッタリング等により保持用SiO2層を
形成する。この厚さは、後に説明する空間層40の厚さ
、下部SiO□層33の厚さ及び圧電体35の厚さの2
の和の厚さにする。フォトリソグラフィ技術によりSi
O□iO□の一部をエツチングする(第2図(a))。
(Example) The manufacturing method of the present invention will be explained with reference to FIG. A holding SiO2 layer is formed on the surface of the silicon substrate 31 by sputtering or the like. This thickness is equal to 2 times the thickness of the space layer 40, the thickness of the lower SiO□ layer 33, and the thickness of the piezoelectric body 35, which will be explained later.
Make the thickness equal to the sum of Si by photolithography technology
A part of O□iO□ is etched (FIG. 2(a)).

薄膜共振部を形成するためエツチング部をZnO等後で
容易にエツチング出来る材料(エツチング材)にて埋め
る(第2図(b))。
In order to form a thin film resonance part, the etched part is filled with a material (etching material) that can be easily etched later, such as ZnO (FIG. 2(b)).

下部SiO□層33をスパッタリング等にて形成し、下
部電極34を真空蒸着法及びフォトリソグラフィ技術に
て形成する(第2図(C))。圧電体35をスパッタリ
ング等で形成し、エツチング法等でバターニングする(
第2図(d))。上部電極36を下部電極34を同様に
形成し、上部SiO□層37をスパッタリング等にて形
成する(第2図(e))。薄膜共振部をマスクし、保持
用SiO□層32、下部SiO□層33及び上部SiO
□層37をフッ酸等にてエツチングし、保持用SiO□
層32エツチング部に埋められたZnO等エツチング材
の端面を露出させる。
A lower SiO□ layer 33 is formed by sputtering or the like, and a lower electrode 34 is formed by vacuum evaporation and photolithography (FIG. 2(C)). The piezoelectric body 35 is formed by sputtering or the like, and patterned by etching or the like (
Figure 2(d)). An upper electrode 36 is formed in the same manner as the lower electrode 34, and an upper SiO□ layer 37 is formed by sputtering or the like (FIG. 2(e)). Masking the thin film resonance part, the holding SiO□ layer 32, the lower SiO□ layer 33 and the upper SiO
□ Etch the layer 37 with hydrofluoric acid etc. to form a retaining SiO□
The end face of the etching material such as ZnO buried in the etched portion of layer 32 is exposed.

(第2図(f))。保持用SiO□層32のエツチング
部に埋められたエツチング材のZnO層を希釈した塩酸
等にてエツチングし、薄膜共振部とシリコン基板とを分
離する空間層40を形成する(第2図(g))。
(Figure 2(f)). The ZnO layer of the etching material buried in the etched portion of the holding SiO□ layer 32 is etched with diluted hydrochloric acid or the like to form a space layer 40 separating the thin film resonant portion and the silicon substrate (see FIG. 2(g)). )).

この時、電極材料により挾まれたZnO等圧電材料及び
さらにその上下面を5i02により挟んだ薄膜共振部は
空間層40によりSi基板と分離され構成される。また
、保持用SiO□層32の厚さを、およそ空間層40の
厚さ、下部SiO□層33の厚さ及び圧電体35の厚さ
の%の和の厚さにすることにより、薄膜共振部の中心面
を保持用SiO□層表面及びその延長線とほぼ一致させ
ることが出来る。
At this time, the ZnO equivalent piezoelectric material sandwiched between the electrode materials and the thin film resonator section whose upper and lower surfaces are sandwiched between 5i02 are separated from the Si substrate by the space layer 40 and configured. Furthermore, by setting the thickness of the holding SiO□ layer 32 to approximately the sum of the thickness of the space layer 40, the thickness of the lower SiO□ layer 33, and the thickness of the piezoelectric body 35, thin film resonance can be achieved. The central plane of the portion can be made to substantially coincide with the surface of the holding SiO□ layer and its extension line.

このように製造すると、通常電極薄膜の厚さは他の薄膜
と比較し充分薄いので、薄膜共振部の全体は厚み方向に
ほぼ対称となり膜界面の歪応力が多層全体では打ち消し
、たわみ、クランクの発生を著しく低減できる。
When manufactured in this way, the thickness of the electrode thin film is usually sufficiently thin compared to other thin films, so the entire thin film resonant part is almost symmetrical in the thickness direction, and the strain stress at the film interface is canceled out by the entire multilayer, resulting in bending and cranking. The occurrence can be significantly reduced.

ここでは31をシリコン基板としたが、フン酸等5iO
zエツチング液にてエツチングされない材料の基板、も
しくはシリコン基板、SiO□基板表面をSiN等フン
酸等5iOzエツチング液にてエツチングされない材料
にてコーティングされた基板にても同様にたわみ、クラ
ックの発生を著しく低減できるのば明らかである。
Here, 31 is a silicon substrate, but 5iO
Similarly, substrates made of materials that cannot be etched with the Z etching solution, or substrates whose surfaces are coated with materials that cannot be etched with the 5iOz etching solution, such as silicon substrates and SiO It is clear that it can be significantly reduced.

また、ここでは薄膜共振部のZnO等の圧電体の上下面
をSiO□層にて挟んだ構造を示したが、特に上下のS
iO□層の無い薄膜共振部を持つ薄膜共振子にても同様
にたわみ、クランクの発生を著しく低減できるのは明ら
かである。
In addition, here we have shown a structure in which the upper and lower surfaces of the piezoelectric material such as ZnO in the thin film resonance part are sandwiched between SiO□ layers, but in particular, the upper and lower S
It is clear that a thin film resonator having a thin film resonator without an iO□ layer can similarly deflect and significantly reduce the occurrence of cranking.

(発明の効果) 以上説明したように、本発明による薄膜共振子は薄膜共
振部の歪応力を分散させる構造及び製造法なので、従来
法において問題となっていた、たわみ、クラック等の発
生を著しく低減させる効果があり、機械的強度の高い、
共振時の特性劣化の少ない薄膜共振子を提供できる。
(Effects of the Invention) As explained above, since the thin film resonator according to the present invention has a structure and a manufacturing method that disperse strain stress in the thin film resonator, the occurrence of deflections, cracks, etc. that have been problems with conventional methods can be significantly reduced. It has a high mechanical strength and has the effect of reducing
A thin film resonator with less characteristic deterioration during resonance can be provided.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の薄膜共振子の断面図、第2図は本発明
の薄膜共振子の製造法の説明図、第3図及び第4図は従
来の薄膜共振子の断面図である。 1]、、21.31・・・シリコン基板、12・・・エ
ピタキシャル層、13・・・SiO□層、14.、 2
,1.、 34・・・下部電極、15.25.35・・
・圧電体、16゜26.36・・・上部電極、23.3
3・・・下部5i02層、上 27.37・・・主部SiO□層、28・・・開口部、
29゜39・・・薄膜共振部保持部、32・・・保持用
SiO□層、40・・・空間層。
FIG. 1 is a sectional view of a thin film resonator of the present invention, FIG. 2 is an explanatory diagram of a method of manufacturing a thin film resonator of the present invention, and FIGS. 3 and 4 are sectional views of a conventional thin film resonator. 1], 21.31...Silicon substrate, 12...Epitaxial layer, 13...SiO□ layer, 14. , 2
,1. , 34...lower electrode, 15.25.35...
・Piezoelectric body, 16°26.36...Top electrode, 23.3
3... Lower part 5i02 layer, upper part 27.37... Main part SiO□ layer, 28... Opening part,
29° 39... Thin film resonant part holding part, 32... SiO□ layer for holding, 40... Space layer.

Claims (2)

【特許請求の範囲】[Claims] 1.基板表面に保持用SiO_2層を形成する手段と、
該保持用SiO_2層の一部をエッチングし、該エッチ
ング部分をZnO等後で容易にエッチングできる材料(
エッチグ材)にて埋める手段と、その上面に電極材料に
て上下面を挟んだZnO等圧電材料、もしくはさらにそ
の上下面をSiO_2層により挟んだ薄膜共振部を形成
する手段と、前記保持用SiO_2エッチグ部に埋めら
れたエッチング材をエッチングすることにより空間層を
つくり、前記薄膜共振部と基板とを分離する手段とを備
えたことを特徴とする薄膜共振子の製造方法。
1. means for forming a holding SiO_2 layer on the substrate surface;
A part of the holding SiO_2 layer is etched, and the etched part is covered with a material that can be easily etched later (such as ZnO).
means for filling with a piezoelectric material such as ZnO whose upper and lower surfaces are sandwiched between electrode materials, or a thin film resonator whose upper and lower surfaces are further sandwiched between SiO_2 layers; 1. A method for manufacturing a thin film resonator, comprising means for separating the thin film resonator and a substrate by etching an etching material buried in the etching portion to create a space layer.
2.特許請求範囲1項の薄膜共振子で、基板表面に形成
するSiO_2層の厚さを薄膜共振部の厚さの1/2よ
り厚くし、さらにエッチング部にエッチング材を埋めた
後の深さが薄膜共振部の厚みの約1/2としたことを特
徴とする薄膜共振子の製造方法。
2. In the thin film resonator according to claim 1, the thickness of the SiO_2 layer formed on the substrate surface is made thicker than 1/2 of the thickness of the thin film resonant part, and the depth after filling the etched part with an etching material is A method of manufacturing a thin film resonator, characterized in that the thickness of the thin film resonator is approximately 1/2 of the thickness of the thin film resonator.
JP63227154A 1988-09-09 1988-09-09 Manufacturing method of thin film resonator Expired - Fee Related JP2657530B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63227154A JP2657530B2 (en) 1988-09-09 1988-09-09 Manufacturing method of thin film resonator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63227154A JP2657530B2 (en) 1988-09-09 1988-09-09 Manufacturing method of thin film resonator

Publications (2)

Publication Number Publication Date
JPH0275210A true JPH0275210A (en) 1990-03-14
JP2657530B2 JP2657530B2 (en) 1997-09-24

Family

ID=16856342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63227154A Expired - Fee Related JP2657530B2 (en) 1988-09-09 1988-09-09 Manufacturing method of thin film resonator

Country Status (1)

Country Link
JP (1) JP2657530B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1557945B1 (en) * 2002-10-28 2010-08-11 Panasonic Corporation Piezoelectric vibrator, filter using same, and method for adjusting piezoelectric vibrator

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6281807A (en) * 1985-10-05 1987-04-15 Toshiba Corp Piezoelectric thin film resonator
JPH01157108A (en) * 1987-12-14 1989-06-20 Victor Co Of Japan Ltd Piezoelectric thin film resonator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6281807A (en) * 1985-10-05 1987-04-15 Toshiba Corp Piezoelectric thin film resonator
JPH01157108A (en) * 1987-12-14 1989-06-20 Victor Co Of Japan Ltd Piezoelectric thin film resonator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1557945B1 (en) * 2002-10-28 2010-08-11 Panasonic Corporation Piezoelectric vibrator, filter using same, and method for adjusting piezoelectric vibrator

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Publication number Publication date
JP2657530B2 (en) 1997-09-24

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