JPH027531B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the configuration of a time measurement circuit that can arbitrarily select a time measurement time.

Generally, when configuring a timer circuit that measures a predetermined time after receiving a timer start input, a frequency divider circuit with a variable frequency division ratio is used if it is desired to arbitrarily select the timer. As an example, FIG. 1 shows a clock circuit that clocks n cycles of an input clock. The clock circuit in the figure includes a frequency divider circuit with a variable frequency division ratio, and a differentiation circuit 1 that detects the passage of one cycle of the output of the final stage of the frequency divider circuit.
and n can be selected from any positive integer from 2 to 10. The frequency dividing circuit with a variable frequency division ratio is composed of five stages of cascaded master-slave type delay flip-flops 2, one NOR circuit 3, one negative logic AND circuit 4, and four AND circuits 5. Differentiator circuit 1 detects the fall of the waveform of Q output _Q4 of the final stage flip-flop and outputs a differential pulse. The timekeeping method is to cancel the reset by changing the reset signal RST from a high level to a low level at the same time as receiving a timekeeping start input, and to count n cycles of the clock signal CLK. n is 2
Any positive integer between ~10 can be set, and the method is to set a signal to data input D ₀ as shown in the table in Figure 2.
It can be selected by connecting any one of T ₁ to T ₉ .

However, if the configuration example shown in Figure 1 is integrated into an integrated circuit with other electronic circuits, and the clocking time can be arbitrarily selected by mask slicing using a mask during the manufacture of the integrated circuit, all the circuits shown in the figure can be integrated. Therefore, since the number of constituent elements is large, the area occupied by the pattern becomes large. In general, the degree of integration of integrated circuits is being improved by reducing pattern dimensions, but when there are multiple types of circuits with the same function, it is clear that circuits with fewer components improve the degree of integration. Therefore, it is necessary to intend to improve the degree of integration from the viewpoint of circuit design.

The present invention has been made to eliminate such drawbacks, and its purpose is to improve the degree of integration by providing a timekeeping circuit that can arbitrarily select a timekeeping time using a minimum number of components.

As an example of the structure of the present invention, FIG. 3 shows a timekeeping circuit that measures time corresponding to m/2 (m=positive integer from 1 to 16) periods of the clock signal CLK. The circuit shown in the figure is a master-slave type delay circuit with three stages connected in cascade.
It consists only of a flip-flop 2 and a differentiating circuit 1 that detects the fall of the output Q of the frequency divider circuit as in FIG. The time according to m is measured. The delay flip-flop 2 has a configuration as shown in FIG. 4, and has a master section output QM, a slave section output Q, a data input D, and a reset input R.
and clock input C correspond to the positions of FIG. 4, respectively. To arbitrarily select m in the circuit of Figure 3, inputs C ₁ and C ₂ of the flip-flop and input DI of the differentiator circuit should be set as shown in the table of Figure 5.
Just connect to one of T ₁₀ to T ₂₁ . As a specific example, the states of each signal when m=10 are shown in the timing diagram of FIG. According to this configuration example, _T10 falls at m/2=5.5 cycles of the input clock CLK after the reset is released, and the pulse detected by the differentiating circuit 1 becomes an output after a set time has been measured. The table below is one connection example, and by arbitrarily combining the signals _T10 to _T21 , it is possible to obtain a frequency division ratio that matches the value of m with other connection combinations.

Comparing FIG. 3 with FIG. 1, it is clear that the present invention is constructed with the minimum necessary elements of a delay flip-flop and a differential circuit, thereby reducing the number of elements. Furthermore, according to the circuit configuration of the present invention, the time measured when n=10 in FIG. 1 is m=20.
The delay flip-flop requires only four stages, further reducing the number of components.

According to the configuration of the present invention, it is possible to freely adapt to the length or shortness of the time measurement simply by increasing the number of stages of flip-flops connected in cascade.Moreover, as is clear from comparing the values of n and m, the resolution of the time measurement is improved. It is characterized by being high. Furthermore, in the present invention, the effect of reducing the number of constituent elements becomes greater as the time measurement time becomes longer.

[Brief explanation of drawings]

FIG. 1 is an example of a time measurement circuit using a conventional frequency division ratio variable frequency divider circuit. FIG. 2 is a connection selection table for the circuit of FIG. FIG. 3 is an example of a timing circuit according to the present invention. Figure 4 shows an example of the configuration of a master-slave type delay flip-flop. Figure 5 shows the third
Connection selection table for the circuit shown in the figure. FIG. 6 is an example of a timing diagram in the circuit of FIG. 3. 1: Differential circuit, 2: Master-slave type delay flip-flop, 3: NOR circuit, 4:
Negative logic AND circuit, 5:AND circuit.

Claims (1)

[Scope of Claims] 1. A timekeeping circuit that starts measuring a predetermined time after receiving a timekeeping start signal, the timekeeping circuit comprising at least two or more stages of master-slave type delay flip-flops connected in cascade; It is composed of a differentiator that differentiates the output signal of a master-slave type delay flip-flop and outputs a timing end signal, and the master-slave type delay flip-flop has a total of four outputs: a master output, a slave output, and each antiphase output The clock input of the master-slave type delay flip-flop in the first stage is inputted with a clock signal for timekeeping, and the clock input of the master-slave type delay flip-flop in the first stage and thereafter is inputted to the clock input of the master-slave type delay flip-flop in the previous stage. A timekeeping circuit characterized in that it is programmably connected to any of the four outputs of a slave type delay flip-flop.