JPH0277683U

JPH0277683U -

Info

Publication number: JPH0277683U
Application number: JP15730588U
Authority: JP
Priority date: 1988-12-02
Filing date: 1988-12-02
Publication date: 1990-06-14

Description

[Brief explanation of drawings]

第１図はこの考案の一実施例を示す図、第２図
は従来の装置を示す図である。図中、１は空中線
、２は受信機、３はＡ／Ｄ変換器、４は掛算器、
５はローパスフイルタ、６は分周器、７はカウン
タ、８はＲＯＭ、９は９０°移相器、１０はミキ
サー、１１はローパスフイルタである。なお図中
、同一符号は、同一又は相当部分を示す。 FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional device. In the figure, 1 is an antenna, 2 is a receiver, 3 is an A/D converter, 4 is a multiplier,
5 is a low-pass filter, 6 is a frequency divider, 7 is a counter, 8 is a ROM, 9 is a 90° phase shifter, 10 is a mixer, and 11 is a low-pass filter. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

An antenna that receives an echo signal from a target, a receiver that down-converts the echo signal received by this antenna and converts it into an intermediate frequency, a frequency divider that converts the output of a coherent oscillator in the receiver into a clock signal, and a frequency divider that converts the output of the coherent oscillator in the receiver into a clock signal. A counter that operates based on the output of the receiver, a ROM that operates using the output of the counter as an address, and an A/D that quantizes the output of the receiver.
a converter, a multiplier that multiplies the digital intermediate frequency signal that is the output of the A/D converter and the digital coherent signal that is the output of the ROM, and a low-pass filter that suppresses the harmonic signal output from the multiplier. A radar device characterized by: