JPH0281324A - Method for correcting reproduced signal - Google Patents

Abstract

PURPOSE:To enable stable data demodulation by previously forming specific pattern parts at the time of information recording, correcting the duty of the reproducing pulses obtd. by binarization of the reproduced signal obtd. from the specific pattern parts by the standard threshold value at the time of reproducing and further correcting the correction error by an increase or decreases of the threshold value. CONSTITUTION:The region where the duty ratio is constant is provided. The reproduced signal 100 obtd. from the pattern region is first binarized by a standard slice level 106 to obtain the reproduced pulses 118 of a digital signal state at the time of reproducing. The duty ratio of the pulses 118 is detected by counting the pulses by count clocks and the reproduced pulses are delayed by as much as the time corresponding to the number of clocks of the deviated component of the duty ratio. The delayed pulses and the original reproduced pulses are ANDed or ORed to correct the duty ratio so as to approximate the ratio to the prescribed duty ratio as far as possible. Further, the component remaining after the correction is absorbed by fine adjustment of the slice level 106. Namely, the correction of the same value is applied to the user data recording region as well. The stable data demodulation is executed in this way.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for setting a threshold value of a reproduction signal in an optical disk device and a correction method for reproduction pulse width or interval, and in particular, it relates to a method for correcting the reproduction pulse width or interval, and in particular, it relates to a method for correcting the fluctuation in pit length or pit interval that occurs during recording. The present invention relates to a reproduced signal correction method that enables stable demodulation even for

[Conventional technology]

Conventionally, as described in JP-A-56-1115024, when generating a threshold value for a reproduced signal, the positive envelope and negative envelope of the signal waveform are detected, and the average value of the levels of both envelopes is calculated. It has been decided as a standard. According to such a threshold value setting circuit, it is possible to correctly binarize even when the direct current component of the signal fluctuates, such as when the signal amplitude fluctuates relatively slowly. However, in optical disk devices and the like, there are cases where a proportional relationship does not hold between the signal amplitude and the optimum slice level due to variations in the recording medium or recording conditions, and a sufficient effect cannot be expected. In such a case, if the 0 level and the level of the reproduced signal occur with equal probability, that is, if the modulation method is highly DC-free, the signal obtained by integrating the output of the comparator for binarization is used as the threshold value. An effective method is to provide negative feedback as an error signal. However, in the case of a modulation method with poor DC-free properties, the average level of the reproduced signal may change suddenly due to the sparseness or density of the data string, so it is conceivable that the above method cannot perform sufficiently accurate demodulation.

Japanese Patent Laid-Open No. 62-254514 proposes a method to solve this problem. That is, by adding an edge detection circuit, a synchronous clock generation circuit, etc. to the slice level setting circuit,
The clock generation circuit generates a reproduced clock synchronized with the previous edge of the reproduced pulse binarized at a certain slice level, and the reproduced pulse is synchronized again with this reproduced clock. Here, by taking a difference signal between the original reproduction pulse and the resynchronized reproduction pulse, it is possible to detect the deviation of the trailing edge position of the reproduction pulse with respect to the reproduction clock. By passing this difference signal through a low-pass filter to generate an error signal and increasing or decreasing the slice level so as to make the error signal zero, the slice level can always be controlled to an optimal value. However, in the above system, the minimum condition for accurate data demodulation is that the variation in the trailing edge position relative to the leading edge position of the reproduced signal is within a distance corresponding to one cycle of the reproduced clock. Since one cycle of the reproduced clock corresponds to the data detection window width, in other words, the edge fluctuation allowed during data recording must necessarily fall within the detection window width. However, in actual recording conditions, fluctuations that exceed the detection window width may occur due to fluctuations in the recording power such as the recording pulse width, fluctuations in the sensitivity of the recording medium, and deviations in the intensity distribution of the recording/reproducing light spot. . FIG. 3 shows an example of a pit recorded on an optical disk, a reproduction signal waveform, and a reproduction pulse that is binarized using the average value of the reproduction signal as a threshold. The pits are recorded on track 310.

FIG. 3(b) shows the case where the target pit length is formed. The example shown in FIG. 3 shows a case where encoded pits are made to correspond to the leading edge and trailing edge of the pit, respectively. Third
In Figure (b), each edge position interval is all detection window @31
This is the case where it corresponds to approximately the center of 2. pit 301
Generally, the reproduced signal 321 decreases in the pit area because the reflectance decreases in the pit area.

Rise between pits. A reproduction pulse 331 is obtained by binarizing this reproduction signal 321 at a slice level 311 which is an average value. As an example, we have shown a case where the reproduced signal is detected as a change in the reflectance of a pit, but there is also a case where a magneto-optical signal is detected as a rotation of the plane of polarization corresponding to the magnetization direction of a magnetized domain, as seen in magneto-optical recording. The same applies to those obtained from recording media other than optical disks. in fact.

As an extreme case due to fluctuations in the recording medium and recording conditions, it is expressed based on the front edge position of the pit.

FIG. 3(a) shows a state in which the pit length is short, and FIG. 3(Q) shows a state in which the pit length becomes long. Figure 3 (
In a), the position of the trailing edge is in front of the detection window width 313 that should be included when the front edge is taken as a reference, and in FIG. This is the case when the position is later. In either case, unless some kind of correction is made, the data will be recognized as different data. If the data pattern is known in advance, the slice level shown in FIG. 3 is increased by increasing it in the case of FIG. 3(a) and decreasing it in the case of FIG. A possible method is to obtain a reproduction pulse 331 as shown in (b). However, if the slopes of the front and rear edges of the reproduced signals 320 to 322 are not sufficiently gentle, it cannot be corrected by simply increasing or decreasing the slice level. On the other hand, if the edges of the reproduced signals 320 to 322 have a gentle slope, there is a risk that fluctuations in the edge positions of the reproduced pulses after slicing may increase due to the influence of noise contained in the signals. For these reasons, conventional slice circuits may not be able to compensate for variations in recording pit length that exceed the detection window width.

[Problem to be solved by the invention]

The above-mentioned conventional technology has a problem in that when there is a large fluctuation in pit length caused by fluctuations in recording conditions during recording, it is not possible to correct the fluctuation time to within the detection window width only by increasing or decreasing the slice level.

The present invention is capable of converting a reproduced signal obtained from a pit string recorded in an area in which a data pattern is known in advance to a standard slice level, for example, by using a recording method that makes edge positions correspond to encoded bits. The digital signal is corrected so that the duty ratio of the binarized reproduced pulse becomes close to a normal value based on the average level of the differential waveform. Furthermore, the remaining correction amount is absorbed by finely adjusting the slice level. Thereby, stable data demodulation can be realized by applying the same amount of correction to the user data recording area.

[Means to solve the problem]

In order to achieve the above object, the data format pattern is provided with an area in which the duty ratio is constant (for example, 50%) in order to suppress large fluctuations in recording pit length to a range that can be absorbed by only fine adjustment of the slice level. This area may also be used as a reproduction clock synchronization pattern sequence. During reproduction, the reproduction signal obtained from the pattern area is first binarized at a standard slice level to obtain a reproduction pulse in the digital signal state. The duty ratio of the reproduced pulse is detected by counting it with a counting clock, the reproduced pulse is delayed by a time corresponding to the number of clocks corresponding to the shift in the duty ratio, and the logical sum of this delayed pulse and the original reproduced pulse ( By performing OR) or logical product (AND), the duty ratio is corrected to approach a predetermined duty ratio. Here, this significant correction will be referred to as macro correction.

If the period of the counting clock is made sufficiently shorter than the data detection window width, the edge position can be kept within the detection window width by macro correction. The user data pattern that follows the macro correction area has a random duty ratio, but in general, in optical disk files that process data in units of sectors, recording conditions rarely vary within the same sector. Therefore, by applying the same correction amount as the macro correction amount to the user data pattern, more accurate data demodulation becomes possible. Furthermore, when recording pit edges, if we look at only the leading edges or trailing edges, the interval between them is not easily affected by the recording conditions.

As a method to absorb minute edge fluctuations that could not be suppressed by macro correction, in the second half of the correction data pattern area,
By detecting the sum of the 0 level duration and the sum of the level duration of the macro correction reproduction pattern as an integral value by an integrating circuit, and using the difference between the integral values as an error signal, the slice level is slightly increased or decreased. More accurate correction is possible. Such fine correction will be referred to as micro correction. Another means of micro-correction is to use a PLL (phase-locked loop) circuit to generate a regenerated clock that is synchronized with the front edge of the regenerated pulse before macro correction, and then generate a pulse that is synchronized with the regenerated clock again. The difference signal between the zero original reproduction pulse and this synchronized reproduction pulse is:

It represents the phase difference between the reproduced clock and the trailing edge of the original reproduced pulse. Therefore, if this difference signal is used as an error signal and is negatively fed back to the slice level, micro-correction is possible. Also, instead of taking the difference signal, the rear edge pulse after macro correction is used as a trigger to generate the 0. By latching the level, it is also possible to detect the phase difference between the rising edge of the trailing edge detection pulse and the rising edge of the reproduced clock as the difference in frequency of occurrence of leading phase pulses and slow phase pulses. Furthermore, there is also a method in which a second slice level is provided separately from the standard slice level for generation of trailing edge detection pulses, and only the second slice level is increased or decreased using the error signal shown in the above-mentioned micro correction method.

[Effect]

The macro correction circuit starts macro correction processing by inputting a gate signal for indicating a correction area from a marker provided at the beginning of the sector format. First, the duty ratio of a reproduced pulse binarized at a standard slice level is detected using a counting clock. The shorter the period of the counting clock, that is, the higher the frequency, the smaller the correction error after clock correction. It is necessary to make the clock cycle shorter than at least the data detection window width. Another criterion for setting the clock frequency is not to increase or decrease the slice level too much in micro-correction. The counting clock is input to the up/down counter, and goes up when the reproduction pulse is 1.

When the macro correction head is completed, the counter value is referred to and the ratio or difference between the 1 and 0 sections of the reproduction pulse is detected.The difference between the count values is set to zero. The amount of delay of the reproduction pulse is selected, and a correction pulse is obtained from the original reproduction pulse and this delayed pulse.

For example, if the count value in the 1 level (H" level) section of the reproduction pulse is 2 clocks more than the count value in the 0 level (''L" level) section, it will correspond to 1 clock. By delaying the reproduction pulse by a certain amount of time and performing a logical product (AND) with the original reproduction pulse, it is possible to shorten the 1 level by 1 clock and lengthen the 0 level by 1 clock, so it can be used as a correction pulse. You can get a duty ratio of almost 50%.On the contrary, only for 2 clocks,
If the 0 level section is longer, a similar correction pulse can be obtained by performing a logical sum (OR) of the pulse delayed by one clock and the original reproduction pulse.

The micro correction circuit includes a method of detecting the duty of the reproduced pulse after macro correction by using an integrating circuit, a method of generating a pulse that is synchronized with the reproduced pulse again using a reproduced clock synchronized with the front edge of the reproduced pulse, A method of detecting the difference between the reproduction pulses and widths of the two using a differential amplifier,
There is a method of detecting the difference in frequency of occurrence of leading phase pulses and delayed phase pulses using a phase comparator.

There is also a method of providing a slice level to be controlled by micro-correction separately from the standard slice level. In other words, another stay level is used to move only the rear edge position forward or backward based on the front edge position.In the 0 hydraulic type, the front edge position does not change even with micro correction, so the regenerated clock is generated only from the front edge. In the case of generation, the response band of the recovered clock generation circuit can be set independently of the band of the micro correction circuit.

〔Example〕

The present invention will be explained in detail below. FIG. 1 is an example of a circuit for reproducing information recorded by a recording method in which a code bit corresponds to the edge position of a recording pit as shown in FIG. 3, and includes a reproduction correction circuit. FIG. 2 is a time chart for explaining the operation of a circuit portion that generates an edge position detection pulse without paying particular attention to reproduction correction. In FIG. 1, a portion corresponding to an optical pickup is omitted in the case of an optical disc, but the configuration of the detection section is not particularly limited. The present invention can be applied to signals obtained from storage means or transmission means other than optical disks as long as they are subject to reproduction correction as the object of the present invention.

This will be explained using FIGS. 1 and 2. Playback signal 100.1
01 is input to the buffer 200 as a differential signal. Although the reproduced signal 101 is not shown in FIG. 2, it is an inverted signal of the reproduced signal 100. The output of the buffer 200 is input to a differentiator 201 to obtain a first-order differential signal. After this,
After being amplified to an appropriate level by an amplifier 202 and passing through a low-pass filter 203, it is inputted again to a buffer 204.
A first-order differential signal 102°103 is obtained as a result output. Here, the buffers 200, 204 and the amplifier 202 may have commonly used configurations.

Further, the differentiator 201 and the low-pass filter 203 may be either passive elements or active elements.

In the case of edge recording, the positive and negative peak positions of the first-order differential signal correspond to the front edge and rear edge positions of the reproduced signal, respectively. In the time chart of FIG. 2, the effects of differential operations and circuit delays are ignored. 1st order differential signal 10
After being further differentiated by a differentiator 205, the signals 2 and 103 pass through an amplifier 206, a low-pass filter 207, and a buffer 208 in the same manner as described above to obtain second-order differential signals 104 and 105. 2
The zero crossing points of the differential signals 104 and 105 correspond to exactly one peak position of the differential signals 102 and 103, and are the edge positions themselves. Comparators 208, 210
Gate pulses 108° 109 are obtained by inputting first-order differential signals 102° 103 to , respectively. Here, the slice level 106 is a threshold value when generating a gate pulse. This gate pulse 108, 109 is the second-order differential signal 104
This is to prevent erroneous pulses generated from points other than the zero loss point of .degree. 105 from being recognized as data. The gate pulses 108 and 109 are inputted to the set (S) terminal and reset (R) terminal of the flip-flop 211, respectively, and outputted to obtain pulses 110° and 111. On the other hand, the second-order differential signal 104°105 indicates the slice setting W! 212. In addition to this, the slice setter 212 also has a slice level 107 as an input. The slice level is
A constant value level 112, which is a macro correction area, is selected by a signal 113 instructing the correction area. Generally, the average level of the second-order differential signals 104 and 105 is selected.Here, the circuit operation before the micro-correction operation will be explained. Comparator 213 is a differential comparator, and second-order differential signal 10
4. Output pulses 114 and 115 for 105.

Further forward, along with the pulses 110 and 111 generated from the first-order differential signals 102 and 103, the flip-flop 2
Pulse 1 to the trigger (T) terminals of 14 and 215, respectively.
14 and pulse 115 are input. This causes pulse 11
The pulse 110 is taken in using the rising edge of the pulse 111 as a trigger, and the pulse 116 is obtained by being reset at the 11 HIt level of the pulse 111. pulse 117
The same applies to Finally, OR gate 21
By 6.

In this embodiment, the rising edge of the reproducing pulse 118 and the falling edge of the reproducing pulse 119 correspond to the edge position. FIG. 5 shows an example of the configuration of the slice setter 212 and the comparator 213. The slice level 107 is applied as a bias voltage to the differential signal 104 via a resistor 502 after the DC component is cut by a capacitor 500 . Also, the differential signal 1
After cutting the DC component with a capacitor 501 as a bias voltage for 05, 1 inversion tank width @ 504 is applied via a resistor 503 to invert the polarity of the slice level 107, and is as shown in the figure. In this case, the input resistance 505 and the feedback resistance 506 have the same value. Comparator 21
Reference numeral 3 is a differential input/output type, and may be one that is generally used as a line receiver.

Next, the sector format for reproduction correction, particularly macro correction, will be explained. FIG. 4(a) is a diagram showing an example of the format structure of a certain sector on the disk. Optical discs generally have a preformat area 400 created in advance when creating the disc, and other data areas 40. ．． It can be divided into 1. Preformat area 4
00 further includes a sector mark 410 for indicating the beginning of the sector, and a VFO (variable frequency oscillator) synchronization pattern 4 for generating a reproduced clock.
11, and addresses 412 where track addresses and sector addresses are recorded.

When the user records data, the data is recorded in the data area 401, and the format of this data area 401 is generally as shown in FIG. 4(b). That is, a VFO synchronization pattern 420, a demodulation synchronization pattern 421 for instructing the start of demodulation of user data. Since the contents of the above-mentioned patterns are already known, detailed explanation will be omitted here.<, VFO synchronization pattern 411
．． In 420, a repeating pattern with a certain duty ratio is generally used. For example, in the case of 2-7 modulation, if the data bit length is T (see), a repeating pattern of 1,5T, which is the closest pattern, is used. This is often done to improve the pull-in characteristics of the PLL, and it is not necessarily the optimal pattern because it is the pattern with the closest pit intervals under the recording conditions.

If there is no problem with the PLL characteristics, 2.
It is considered desirable to repeat OT or repeat the pattern with a longer pattern length. Macro correction detects the duty ratio of the reproduced pulses 118 and 119 binarized by a standard slice level, for example, the aforementioned slice level 112, and causes the reproduced pulse width to approach the target duty ratio by delay correction. For example, VFO synchronization pattern etc. has a duty ratio of 50%.
Since this is a pattern that should be recorded in this area, the objective of the macro correction can be achieved by correcting the duty ratio of the reproduction pulse in this portion to approximately 50%. Furthermore, once the amount of macro correction is determined, it is sufficient to correct other data patterns within the same sector by the same amount. This is because the recording conditions are considered to be almost constant within the same sector. For example, if a certain sector originally has a duty ratio of 5.
If a data pattern that should be 0% is recorded and the pit length becomes shorter as shown in Figure 3 (,), then at least the pit length for the data pattern in the same sector has also become shorter by the same amount. This is a correction method based on Of course, if a specific pattern such as a resynchronization pattern that does not depend on user data or a pattern in which the duty ratio is constant is inserted into the user data area 422, macro correction can also be performed in this area. FIG. 4(c) shows a pattern area 430 for macro correction before the VF○ synchronization pattern 420.
This is an example format with . In this case, although the overhead increases slightly, the VFO synchronization pattern 420 uses repeating of the close-packed pattern to improve the pull-in characteristic.
It is also possible to stabilize recording by using a repeating pattern with a slightly longer period in the macro correction area 430.

Now, macro correction will be explained below using FIGS. 6 and 7. FIG. 6 is a configuration example of the macro reproduction correction circuit 217, and FIG. 7 is a time chart showing the operation of the circuit.

The correction area gate 600 is a signal indicating a macro correction area, and can be generated from the sector mark 410 in the format shown in FIG. Since it is generally difficult to completely synchronize the correction area gate 600 with the data signal, the correction area gate 60o is input to the enable (E) of the counter 700 so that the gate signal 600 is "H".
Synchronization can be achieved by using the rising edge of the data pulse 601 as a counting clock only during the section ``.The data pulse 601 and its inverted signal 602 can be generated from the reproduction pulses 118 and 119 described above.

In FIG. 7, from the second-order differential signal 104 to the front edge pulse 55
0. Although the rear edge pulse 551 is generated and the data pulses 601 and 602 are generated using a flip-flop or the like, the same effect can be obtained if the data pulses 601 and 602 are generated using the reproduction pulse 118 or 119 shown in FIG. Output Q of counter 700. 6
03°Q, 604, Qa605 are respectively 2° 21,
2! It supports bit output. First of all, Q. 603 is “
When it reaches H” level, the output Q of flip-flop 701
606 becomes "H". After that, in the example of FIG. 6, the output of the counter 700 is 11511, that is, Q, 603 is "H", Q and 604 are "L", and IIQ2605 is IIH.
The moment it becomes II, the flip-flop 701 is reset and the output Q606 becomes "L". Further, the data pulse 602 is input to the trigger (T) terminal of the flip-flop 702, and after the output Q606 becomes 'H', the flip-flop 702 is set at the rising edge of the first data pulse 602, and the output Q6o7 becomes H''.

After that, when the output 606 becomes "L", the output 607
returns to “L”. Additionally, AND gates 703 and 704 generate signals 608 and 609 for selecting the count-up and count-down states of counter 705, respectively.

That is, when the reproduced signal 100 is on the unrecorded level side (high level in the figure), the counter 705 is in a count-up state, and conversely, when the reproduced signal 100 is on the bit level side (low level in the figure), the counter 705 is in a count-up state. 705 enters a countdown state. Data pulse 601 (602)
A counting clock 610 for measuring the duty ratio of is input to the clock (CK) terminal of the counter 705. However, when neither the count up nor count down state is selected, the clock 610 is not input. In the example of FIG. 6, four periods of data pulses 601 (602) are counted by the clock 610. The state of the output value of the counter 705 is shown as a counter output value 611. The value of the output value 611 is finally "10'" in hexadecimal.

In FIG. 7, upper digits are omitted. In the macro correction process, the output value 611 is divided by 8, which is twice the period of the data pulse 601 (602), that is, the counting clock 61
By increasing or decreasing the width of the data pulse 601 (602) by two cycles of 0, a correction pulse with a duty ratio of 50% can be obtained. In FIG. 7, the 11 HII level section of the data pulse 601 is as long as the 11 L'' level section. -1 (corresponding to 22 to 2N-1 respectively)
, the selector 707 selects a pulse delayed by a time equivalent to two periods of the counting clock 610, and this delayed pulse 612 and the original data pulse 601 are connected to the AND gate 7.
A logical product (AND) is obtained in step 08, and this is output as macro correction data 613 and 614. Suppose that the ILH” level section of the data pulse 601 is 11L.
``If it is shorter than the level interval, conversely, the data pulse 60
1 and the delayed pulse 612 using an OR gate 709, macro correction data can be similarly obtained. Note that in the latter case, the output value 611 of the counter 705 ultimately becomes negative, so the most significant bit QN of the output value 611 is used as the sign bit, and the selector 71
At 0.

Either the output of the AND gate 708 or the output of the ○R gate 7o9 can be selected. As mentioned above, by using a signal whose duty ratio is known in advance, the duty ratio of the data pulse obtained therefrom can be brought close to a predetermined value.9 In Fig. 7, the duty ratio is 50. We have shown the case where the correction is made to be close to %, but
If a certain value is added or subtracted from the counter output value 611 in advance for other duty ratios,
Macro correction is possible with a similar circuit configuration.

Next, for the correction pulses 613 and 614 after Marok correction,
Micro-correction that performs more detailed duty ratio correction will be explained. 8, 10, and 11 show examples of the micro correction circuit 218.

The corresponding time charts are shown in Figures 9 and 12, respectively.
It is shown in FIG. In the example of FIG. 8, the correction pulse 613
, 614 are integrated over the II and HII level sections of the pulses using integrators 800 and 801, and the difference is used as an error signal to control the slice level 107, thereby determining the duty ratios of the correction pulses 613 and 614 in more detail. This is an example of a configuration of a method that approaches 50%. In FIG. 9, macro correction regarding the generation of correction pulses 613 and 614 is the same as that described in FIGS. 6 and 7. The micro correction gate 900 is output after the macro correction is completed, and can be generated in the same way as the macro correction gate 600. The control signal 901 controls the gate 90
Correction pulse 613 immediately after 0 becomes 11 HIT
The rising edge of becomes 11 HII, and after counting the period of the correction pulse 613 or 614 for a predetermined number, it returns to 'L''.Switch the switches 803 and 804 to the signal side only during the period in which the control signal 901 is It H13. The values of the "H" section of the correction pulses 613 and 614 are integrated respectively.The integral output 902 of the integrator 801 (802)
(903) is input to the differential amplifier 805, and the difference signal 9
04 is output. During the period in which the control signal 901 is H'', the sample hold becomes a sample operation, and the difference signal 901 becomes a sample operation.
04 is taken in, and its value is held while the control signal 901 is "L". Note that the control signal 901 discharges the charges stored in the capacitances 801 and 802 in the interval of (i L 11 or other than the start of the data recording area. As a result, the amount of correction in the immediately preceding sector does not affect the control signal 901. As another example of micro correction, the circuit configuration shown in FIG. 10 will be explained together with the time chart shown in FIG. 12.

The correction data 613 is input to a front edge detector 750 and a rising edge pulse 650 is generated.

The edge pulse 650 is generated using correction data 6.
It is sufficient to perform a logical product (AND) of the inverted pulse of the pulse 13 slightly delayed and the original pulse 613. The pulse 650 is input to a phase comparator 751 to detect the phase error with the recovered clock 652, and this error signal 651 is passed through a low-pass filter 752 to a VCO (voltage converter).
control oscillator) 753 as a control signal. The VCO 753 is an element whose oscillation frequency can be varied depending on the value of the input voltage. Generally, the circuit comprised from the phase comparator 751 to the VCO 753 is called a PLL (phase locked loop) circuit 754. PLL
A recovered clock 652 synchronized with the leading edge of the correction pulse 613 can be obtained by the circuit 754. In the circuit shown in FIG. 10, an error signal for controlling the slice level 107 is generated in the following manner when performing micro correction processing. The macro-corrected pulse 613 is input to the delay (D) terminal of the flip-flop 754, and the reproduced clock 6
Rise of the 52 inversion pulse.

That is, resynchronization is performed at the falling edge of the regenerated clock 652 to obtain a synchronization pulse 653.

The circuit example in FIG. 1O shows a PLL circuit in which the phases of the rising edge of the correction pulse 613 and the rising edge of the recovered clock 652 are aligned, and in this case, resynchronization is performed at the falling edge of the recovered clock 652. become By doing this, the pulse width of the synchronization pulse 653 becomes an integral multiple of the period of the reproduction clock 652. Originally,
Since the interval between the rising edge and the falling edge of the reproduced signal 100 must be an integral multiple of the reproduced clock period, the synchronization pulse 653 and the correction pulse 61
The difference in width from 3 corresponds to the remaining amount of correction in macro correction. Therefore, the synchronization pulse 653 and the correction pulse 61
After obtaining the difference signal 654 with 3 by the differential amplifier 755,
By smoothing the waveform with a low-pass filter 756, an error signal 655 is obtained. Micro-correction can be performed by controlling the slice level 107 using the error signal 655.

Next, micro correction processing using the circuit example shown in FIG. 11 will be explained with reference to the time chart shown in FIG. 13. The PLL circuit 754 generates reproduced clocks 660 and 661 that are synchronized with the rising edge of the leading edge pulse 650 of the corrected pulse 613 after macro correction processing, while the trailing edge detector 760 generates the trailing edge pulse 662 of the corrected pulse 613. Here, at the rising edge of the rear edge pulse 662, the level of the reproduced clock 660 is changed to the level of the flip-flop 761.
By latching, a slow phase pulse 663 is obtained.

The pulse width of the slow phase pulse 663 is equal to that of the rear edge pulse 662.
It represents the phase difference between the rising edge of the clock and the rising edge of the reproduced clock. Similarly, by latching the recovered clock 661 at the rising edge of the trailing edge pulse 662, a phase advance pulse 664 can be generated. A differential amplifier 763 generates a difference signal between leading and lagging pulses, and this is passed through a low-pass filter 764.
By smoothing with , an error signal 655 is obtained.

An additional note will be made regarding the method of controlling the slice level 107 using the error signal 655. If the slope of the rise and fall of the second-order differential signal 104 is θ, the binarized pulse 601 corresponds to the slice level being shifted by Ve,
The pulse width change Te of 602 is given by the following equation.

te=Ve/lanθ Here, it is assumed that the slope of the second-order differential signal 104 near the zero crossing point can be approximated by a straight line. Therefore, the differential amplifier 7
By appropriately setting the gains of 55 and 763 according to the slope θ, micro correction can be performed.

The method shown in FIG. 14 is similar to the methods shown in FIGS. 11 and 13 up to the generation of the slow phase pulse 663 and the advanced phase pulse 664. In the method of FIG. 14, the difference signal 655 controls the second slice level 850 instead of the first slice level 107. 2nd slice level 8
50 is a binarized pulse 60 obtained from the second-order differential signal 104
1 is used to control only the rear edge position back and forth. Specifically, generation of the correction pulse 613, that is, macro correction, is performed at the first slice level 107.

The rear edge position of the correction pulse 613 is moved back and forth as a micro correction process after passing through the macro correction area.

FIG. 15 shows a pulse 613 in which only the rear edge position is corrected from the correction pulse 613 by the second slice level 850.
This is an example of a circuit for obtaining ′. Comparator 870 selects the second
The second-order differential signal 104 is binarized at a slice level 850. After this, the edge pulse 851 after the binarized pulse is passed through the inverter 872, the delay element 671, and the AND gate 87.
It is generated by a circuit consisting of 3. On the other hand, the flip-flop 874 outputs Q at the rising edge of the correction pulse 613.
becomes "H" and then returns to "L" by resetting with the trailing edge pulse 851, thereby making it possible to correct only the trailing edge position. After the macro correction is completed, micro correction may be performed using the correction pulse 613'.

As an example of reproduction correction, threshold control in the second-order differential detection method has been explained using the edge recording method as an example. This can be similarly realized for a detection method that uses the same method.

〔Effect of the invention〕

According to the present invention, it is possible to suppress fluctuations in recording pit or recording domain length caused by fluctuations in recording pitch, fluctuations in recording characteristics of the medium, etc. during reproduction. In addition, it is possible to effectively suppress large fluctuations during recording that are difficult to correct only by increasing or decreasing the slice level, so stable data demodulation can be achieved.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing an embodiment of the present invention, Figure 2 is a time chart of the second-order differential detection method, Figure 3 is a diagram explaining pit length fluctuations during recording, and Figure 4 is an example of format configuration. FIG. 5 is a diagram showing an example of a slice setting circuit, FIG. 6 is a diagram showing an example of a macro correction circuit, FIG. 7 is a time chart of FIG. 6, FIGS. Figure 11 is a diagram showing an example of a micro correction circuit, Figures 9, 12, and 13.
The figures are time charts showing the operation of the circuits in Figs. 8, 10, and 11, respectively; Fig. 14 is a time chart showing another example of micro correction; and Fig. 15 is a diagram showing an example of the circuit configuration. be. Description of symbols 100.101... Reproduction signal, 217... Macro corrector, 218... Micro corrector, 430... Macro correction area. Mele branch α- 77th? 7th country de θl 8th day B2 Figure 7υ%7/Figure 72nd 73rd

Claims (1)

[Claims] 1. In an apparatus for recording information by forming a recording area on a medium in a state physically different from an unrecorded area, and reproducing the recording area, a specific pattern is used when recording information. By forming a section in advance, and correcting the duty of the binarized reproduction pulse of the reproduction signal obtained from the specific pattern section at the time of reproduction using a standard threshold value, and further correcting the correction error by increasing or decreasing the threshold value. A reproduced signal correction method characterized by absorbing fluctuations in the length or interval of the recording area caused by fluctuations in recording conditions. 2. The above specific pattern also serves as a pattern for synchronizing the reproduced clock, and the duty of the reproduced pulse obtained by binarizing the reproduced signal of the pattern with a standard threshold value is detected by the counting clock. 2. The reproduction signal correction method according to claim 1, wherein the reproduction pulse width is corrected. 3. Generating an error signal for controlling the increase/decrease of the threshold value from the difference between the duty of the reproduction pulse of the level 1 of the reproduction pulse and the level 1 of the inverted pulse of the reproduction pulse, each integrated over a certain period. The reproduced signal correction method according to claim 1, characterized in that: 4. Claim 1, wherein the error signal for controlling the increase or decrease of the threshold value is generated from the phase difference between the phase of a reproduced clock synchronized with the leading edge of the reproduced pulse and the phase of the trailing edge of the reproduced pulse. The reproduced signal correction method described. 5. Claim 1, characterized in that a second threshold for controlling only the trailing edge position of the reproduction pulse is provided separately from the standard threshold, and an error signal for controlling increase/decrease of the second threshold is generated. 5. The reproduced signal correction method according to any one of 4.