JPH0281463A - Cooled mounting structure of semiconductor device and method of cooling - Google Patents
Cooled mounting structure of semiconductor device and method of coolingInfo
- Publication number
- JPH0281463A JPH0281463A JP63231828A JP23182888A JPH0281463A JP H0281463 A JPH0281463 A JP H0281463A JP 63231828 A JP63231828 A JP 63231828A JP 23182888 A JP23182888 A JP 23182888A JP H0281463 A JPH0281463 A JP H0281463A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- wiring board
- cooling
- semiconductor
- gap
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/306—Assembling printed circuits with electric components, e.g. with resistors with lead-in-hole components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Structure Of Printed Boards (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は集積回路の半導体チップから発生する熱を効率
良く除去することができる半導体装置の冷却実装構造お
よび冷却方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a cooling mounting structure and cooling method for a semiconductor device that can efficiently remove heat generated from a semiconductor chip of an integrated circuit.
近年の大型計算機においては、高速データ処理が要求さ
れるため、素子の高集積化が進み、一つの集積回路から
発生する熱量も飛躍的に増大してきた。このため、従来
は問題とされなかった集積回路の過剰な温度上昇が)懸
念され、集積回路の冷却が大型計算機実装での重要な課
題となってきた。In recent years, large-scale computers require high-speed data processing, and as a result, devices have become highly integrated, and the amount of heat generated from one integrated circuit has increased dramatically. For this reason, there are concerns about excessive temperature rise in integrated circuits, which has not been considered a problem in the past, and cooling of integrated circuits has become an important issue when implementing large-scale computers.
半導体チップから発生した熱を放出するために、従来さ
まざまの手段が行なねれている。標準的な冷却技術とし
て強制空冷法が行なわれている。この強制空冷法の1つ
として、集積回路の半導体パッケージの上部に放熱フィ
ンを設け、半導体チップから発生した熱を放熱フィンに
伝達するとともに、この放熱フィンを強制的に空冷して
冷却するようにしたものが知られている(例えば、[電
子通信学会誌JVoQ、65 No、7.(1982
年)。Various methods have been used in the past to dissipate heat generated from semiconductor chips. Forced air cooling is a standard cooling technique. One of these forced air cooling methods is to provide a heat dissipation fin on the top of the integrated circuit semiconductor package, transfer the heat generated from the semiconductor chip to the heat dissipation fin, and cool the heat dissipation fin by forced air cooling. (For example, [Journal of Electronics and Communication Engineers JVoQ, 65 No. 7.
Year).
第748頁から第753頁)。(pp. 748 to 753).
また、第7図に示すように、半導体チップ4で発生した
熱をベルチェ素子10を用いて一相電力に変換したのち
、再び熱に戻して、この熱を入出力ピン3に伝達すると
ともに、人出力ビン3を空冷で冷却するようにしたもの
が提案されている(アイ・ビー・エム テクニカル デ
ィスクロージャー プルテン Vo12,27 No
、9.(1985年)、第5096頁から第5099頁
(IBMTechnical Disclosure
Bulletin VaQ、 27No、9.(19
82)、pp5096−5099))。Further, as shown in FIG. 7, the heat generated in the semiconductor chip 4 is converted into one-phase power using the Bertier element 10, and then returned to heat, and this heat is transferred to the input/output pin 3. It has been proposed that the human output bin 3 is cooled by air cooling (IBM Technical Disclosure Pluten Vo12, 27 No.
,9. (1985), pp. 5096-5099 (IBM Technical Disclosure
Bulletin VaQ, 27 No. 9. (19
82), pp5096-5099)).
〔発明が解決しようとする課題〕
しかしながら、上記従来技術のうち、放熱フィンを設け
たものでは、放熱用フィンの接合が集積回路パッケージ
上面に限定されるため、半導体チップを充分に冷却する
ためには過大な空気量を必要とする。そして、空気量を
増大させると、雑音の問題が生じその実用性は限界に達
している。[Problems to be Solved by the Invention] However, among the above-mentioned conventional technologies, in those in which heat dissipation fins are provided, the bonding of the heat dissipation fins is limited to the top surface of the integrated circuit package, so it is difficult to sufficiently cool the semiconductor chip. requires an excessive amount of air. When the amount of air is increased, a noise problem arises, and its practicality has reached its limit.
また、ベルチェ素子10を用いたものでは、ぺルチェ素
子の使用により装置が複雑化して、コストおよび信頼性
の面で不利であった。Furthermore, in the case of using the Vertier element 10, the use of the Peltier element complicates the apparatus, which is disadvantageous in terms of cost and reliability.
本発明の目的は、簡単な構造で充分な冷却性能が期待で
きる半導体装置の冷却実装構造および冷却方法を提供す
ることである。An object of the present invention is to provide a cooling mounting structure and a cooling method for a semiconductor device that can be expected to have sufficient cooling performance with a simple structure.
上記目的を達成するために、本発明は、少なくとも1つ
の半導体チップを搭載し多数の入出力ピンを有する半導
体パッケージを、配線基板上に設置するとともに、前記
半導体パッケージと前記配線基板との間に空隙を形成し
、該空隙内に冷媒を流して前記半導体チップを冷却する
半導体装置の冷却実装構造において、前記冷媒が流れる
孔を、前記半導体パッケージに対向させて前記配線基板
に穿設したものである。In order to achieve the above object, the present invention provides a semiconductor package that is equipped with at least one semiconductor chip and has a large number of input/output pins, is installed on a wiring board, and is provided between the semiconductor package and the wiring board. In a cooling mounting structure for a semiconductor device in which a gap is formed and a coolant flows into the gap to cool the semiconductor chip, a hole through which the coolant flows is formed in the wiring board so as to face the semiconductor package. be.
また、本発明は、少なくとも1つの半導体チップを搭載
し多数の入出力ピンを有する半導体パッケージを、配線
基板上に設置するとともに、前記半導体パッケージと前
記配線基板との間に空隙を形成し、該空隙内に冷媒を流
して前記半導体チップを冷却する半導体装置の冷却実装
構造において、前記冷媒が流れる孔を、前記半導体パッ
ケージに対向させて前記配線基板に穿設するとともに、
前記半導体パッケージに冷却フィンを設けたものである
。Further, the present invention provides a semiconductor package having at least one semiconductor chip mounted thereon and having a large number of input/output pins, installed on a wiring board, and forming a gap between the semiconductor package and the wiring board. In a cooling mounting structure for a semiconductor device in which the semiconductor chip is cooled by flowing a coolant into a gap, a hole through which the coolant flows is formed in the wiring board so as to face the semiconductor package;
The semiconductor package is provided with cooling fins.
また、本発明は、少なくとも1つの半導体チップを搭載
し多数の入出力ピンを有する半導体パッケージを、配線
基板上に設置するとともに、前記半導体パッケージと前
記配線基板との間に空隙を形成し、該空隙内に冷媒を流
して前記半導体チップを冷却する半導体装置の冷却実装
構造において、前記冷媒が流れる孔を、前記半導体パッ
ケージに対向させて前記配線基板に穿設するとともに、
前記半導体パッケージの入出力ピンの基部に冷却フィン
を設けものである。Further, the present invention provides a semiconductor package having at least one semiconductor chip mounted thereon and having a large number of input/output pins, installed on a wiring board, and forming a gap between the semiconductor package and the wiring board. In a cooling mounting structure for a semiconductor device in which the semiconductor chip is cooled by flowing a coolant into a gap, a hole through which the coolant flows is formed in the wiring board so as to face the semiconductor package;
Cooling fins are provided at the base of the input/output pins of the semiconductor package.
また1本発明は、少なくとも1つの半導体チップを搭載
し多数の入出力ピンを有する半導体パッケージを、配線
基板上に設置するとともに、前記半導体パッケージと前
記配線基板との間に空隙を形成し、該空隙内に冷媒を流
して前記半導体チップを冷却する半導体装置の冷却実装
構造において、前記冷媒が流れる斜めの孔を、前記半導
体パッケージに対向させて前記配線基板に穿設するとと
もに、前記孔へ前記冷媒を導くためのガイド板を形成し
たものである。Further, in the present invention, a semiconductor package mounted with at least one semiconductor chip and having a large number of input/output pins is installed on a wiring board, and a gap is formed between the semiconductor package and the wiring board, and In a cooling mounting structure for a semiconductor device in which the semiconductor chip is cooled by flowing a coolant into an air gap, an oblique hole through which the coolant flows is formed in the wiring board so as to face the semiconductor package, and A guide plate is formed to guide the refrigerant.
さらに、本発明は、半導体チップを搭載した半導体パッ
ケージと該半導体パッケージが設置された配線基板との
間の空隙内に、冷媒を流すことによって前記半導体チッ
プの冷却を行なう半導体装置の冷却方法において、前記
配線基板に穿設された孔を介して、前記半導体パッケー
ジの入出力ピン側に前記冷媒を導入し、この導入された
冷媒が前記空隙内を流れる際に前記半導体チップと冷媒
との間で、熱交換を行なわせるようにしたことである。Furthermore, the present invention provides a method for cooling a semiconductor device in which the semiconductor chip is cooled by flowing a refrigerant into a gap between a semiconductor package on which a semiconductor chip is mounted and a wiring board on which the semiconductor package is installed. The refrigerant is introduced into the input/output pin side of the semiconductor package through the hole formed in the wiring board, and when the introduced refrigerant flows through the gap, the refrigerant cools between the semiconductor chip and the refrigerant. , to allow heat exchange to take place.
また、本発明は、半導体パッケージを搭載した半導体パ
ッケージと該半導体パッケージが11された配線基板と
の間の空隙内に、冷媒を流すことによって前記半導体チ
ップの冷却を行なう半導体装置の冷却方法において、前
記半導体パッケージに上方より前記冷媒を流して、該冷
媒を前記半導体パッケージの入出力ピン側に導入し、こ
の導入された冷媒が前記空隙内を流れる際に前記半導体
チップと冷媒との間で、熱交換を行なわせたのち、前記
配線基板に穿設された孔を介して前記冷媒を排出するよ
うにしたことである。The present invention also provides a method for cooling a semiconductor device in which the semiconductor chip is cooled by flowing a refrigerant into a gap between a semiconductor package on which a semiconductor package is mounted and a wiring board on which the semiconductor package is attached. The coolant is caused to flow into the semiconductor package from above and introduced into the input/output pin side of the semiconductor package, and when the introduced coolant flows through the gap, between the semiconductor chip and the coolant, After the heat exchange is performed, the refrigerant is discharged through the hole formed in the wiring board.
さらに1本発明は、少なくとも一層以上の導電層と、入
出力ピン用のスルーホールとを有する配線基板において
、冷却媒体の流路となる孔が穿設されたものである。Furthermore, one aspect of the present invention is a wiring board having at least one conductive layer and through holes for input/output pins, in which holes are formed to serve as flow paths for a cooling medium.
上記したように、半導体パッケージに対向させて配線基
板に孔を穿設しておけば、冷媒が配線基板に垂直な方向
に流れた場合、該孔を介して冷媒が流れ、半導体パッケ
ージおよび入出力ピンを均一に冷却することができ、冷
却効率が向上する。As mentioned above, if a hole is made in the wiring board facing the semiconductor package, when the coolant flows in a direction perpendicular to the wiring board, the coolant will flow through the hole, and the semiconductor package and input/output The pins can be cooled uniformly, improving cooling efficiency.
また、半導体パッケージまたは入出力ピンの基部に冷却
フィンを設けておけば、冷却効率がより一層向上する。Furthermore, if cooling fins are provided at the base of the semiconductor package or the input/output pins, cooling efficiency can be further improved.
また、配線基板に斜めの孔を穿設するとともに、ガイド
板を設けておけば、冷媒が配線基板に平行な方向に流れ
た場合、ガイド板によって冷媒は斜めの孔内へ導入され
て、半導体パッケージおよび入出力ピンを効率良く冷却
することができる。Additionally, if diagonal holes are drilled in the wiring board and a guide plate is provided, when the coolant flows in a direction parallel to the wiring board, the guide plate will guide the coolant into the diagonal hole, allowing the semiconductor The package and input/output pins can be efficiently cooled.
さらに、冷媒を配線基板に垂直な方向に流すには、半導
体パッケージの上面側から流す場合と、半導体パッケー
ジの下面側すなわち配線基板の裏面から流す場合とが考
えられる。Further, in order to flow the coolant in a direction perpendicular to the wiring board, there are two possible ways to flow the coolant: from the top side of the semiconductor package, and from the bottom side of the semiconductor package, that is, from the back side of the wiring board.
以下に本発明の一実施例を図面に従って説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図において、半導体チップ4は多数の導電層および
絶縁層からなる多層基板11上に搭載され球状の半田ボ
ール5によって電気的に接続されている。また、多層基
板11上に搭載された半導体チップ4はセラミック材料
等によって封止され半導体パッケージ2を形成している
。配線基板1に向かい合っている半導体パッケージ2の
面には。In FIG. 1, a semiconductor chip 4 is mounted on a multilayer substrate 11 consisting of a large number of conductive layers and insulating layers, and is electrically connected by spherical solder balls 5. As shown in FIG. Further, the semiconductor chip 4 mounted on the multilayer substrate 11 is sealed with a ceramic material or the like to form the semiconductor package 2. On the surface of the semiconductor package 2 facing the wiring board 1.
血中央部を除き半導体チップ4に電気的に接続された多
数の入出力ピン3が取付けられている。更に、半導体パ
ッケージ2に取付けられた入出力ピン3の先端は多層基
板から成る配線基板1に銀ロー付は等によって接続され
ている。このとき、半導体パッケージ2と配線基板1と
の間には適当な空隙7が確保される。また、半導体パッ
ケージ2の下部に位置する配線基板1には、冷媒の通路
と成る孔6が開けられている。A large number of input/output pins 3 electrically connected to the semiconductor chip 4 are attached except for the central part of the blood. Furthermore, the tips of the input/output pins 3 attached to the semiconductor package 2 are connected to a wiring board 1 made of a multilayer board by silver brazing or the like. At this time, an appropriate gap 7 is secured between the semiconductor package 2 and the wiring board 1. Further, the wiring board 1 located at the bottom of the semiconductor package 2 is provided with a hole 6 that serves as a coolant passage.
第2図は、第1図の■−■線に沿った断面図である。配
線基板1の半導体パッケージ2に対向する面の中央部に
冷却媒体の通路と成る孔6は開けられている。FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1. A hole 6, which serves as a passage for a cooling medium, is formed in the center of the surface of the wiring board 1 facing the semiconductor package 2.
運転時において、半導体チップ4において発生した熱は
、半田ボール5および多層基板11に伝熱し半導体パッ
ケージ2全体に伝えられる。さらに、入出力ピン3およ
び大気中へと伝わる。一方。During operation, heat generated in the semiconductor chip 4 is transferred to the solder balls 5 and the multilayer substrate 11, and then to the entire semiconductor package 2. Furthermore, it is transmitted to the input/output pin 3 and to the atmosphere. on the other hand.
配線基板1真面に吹き付けられた冷媒は、孔6より空隙
7に流入し半導体パッケージ2の裏面および人出力ピン
3の周面において熱交換を行ない配線基板1から流れ去
る。この一連の過程により、半導体チップは効果的に冷
却される。The coolant sprayed directly onto the wiring board 1 flows into the gap 7 through the hole 6, exchanges heat with the back surface of the semiconductor package 2 and the circumferential surface of the output pin 3, and flows away from the wiring board 1. Through this series of steps, the semiconductor chip is effectively cooled.
第3図は、1個の半導体パッケージ2に対して冷媒導入
用孔6を複数個設けたものである。前記実施例と同様に
配線基板1の裏面に冷媒を噴射し、冷媒を空隙7に導入
して半導体パッケージ2の裏面および入出力ピン3の周
面において熱交換を行なわせる。FIG. 3 shows a semiconductor package 2 in which a plurality of coolant introduction holes 6 are provided. Similar to the embodiment described above, a refrigerant is injected onto the back surface of the wiring board 1 and introduced into the gap 7 to cause heat exchange between the back surface of the semiconductor package 2 and the circumferential surface of the input/output pins 3.
本実施例によれば、孔6を複数個にすることにより冷却
の効率を高めると共に、配線基板1に1個の大きな孔を
開けることにより配線基板1内の導電層の配置に制約を
与えることを回避し、冷却に必要な流量を確保すること
ができる。According to this embodiment, by providing a plurality of holes 6, the cooling efficiency is increased, and by making one large hole in the wiring board 1, the arrangement of the conductive layer in the wiring board 1 is restricted. It is possible to avoid this and secure the flow rate necessary for cooling.
第4図は、第1図に示した実施例において半4体パッケ
ージ2に冷却フィン8を取付けたものである。この実施
例では、配線基板1の裏面に冷媒を噴射し、空隙7に導
入し半導体パッケージ2の裏面および入出力ピン3の周
面において熱交換を行なわせた後、半導体パッケージ2
上面および側面に伝えられた熱を冷却フィン8から奪う
ことによってさらに冷却性能を高めた例である。FIG. 4 shows the embodiment shown in FIG. 1 in which cooling fins 8 are attached to the half-quad package 2. In FIG. In this embodiment, a refrigerant is injected onto the back surface of the wiring board 1 and introduced into the gap 7 to perform heat exchange on the back surface of the semiconductor package 2 and the circumferential surface of the input/output pins 3.
This is an example in which the cooling performance is further improved by removing the heat transferred to the top and side surfaces from the cooling fins 8.
第5図は、第1図に示した実施例において人出カピン3
の基部に冷却フィン8Aを設けたものである。このよう
にすると、入出力ピン3の周囲の放熱面積が大きくなり
、空隙7を流れる冷媒によって入出力ピン3を効率良く
冷却することができる。FIG. 5 shows the number of people in the embodiment shown in FIG. 1.
Cooling fins 8A are provided at the base of the cooling fin 8A. In this way, the heat dissipation area around the input/output pin 3 becomes large, and the input/output pin 3 can be efficiently cooled by the refrigerant flowing through the gap 7.
第6図は、配線基板1に斜めの孔6Aを穿設するととも
に、孔6Aへの冷却媒体の流入を助けるガイド板9を設
置したものである。本実施例においては、冷却媒体の流
入を助けるガイド板9を設けることにより、配線基板l
に沿って冷却媒体が流れている場合においても空隙7へ
の冷却媒体の流入量を確保し効率的に冷却を行なうよう
にした。In FIG. 6, diagonal holes 6A are bored in the wiring board 1, and a guide plate 9 is installed to help the cooling medium flow into the holes 6A. In this embodiment, by providing a guide plate 9 that helps the cooling medium flow, the wiring board l
Even when the cooling medium is flowing along the gap 7, the amount of cooling medium flowing into the gap 7 is ensured to perform efficient cooling.
本実施例は多数の半導体パッケージ2が搭載されている
配線基板1が多数平行に設置されていて、配線基板1に
向かい合う位置に冷却媒体の供給装置が設置できないよ
うな場合に効果的である。This embodiment is effective when a large number of wiring boards 1 on which a large number of semiconductor packages 2 are mounted are installed in parallel, and a cooling medium supply device cannot be installed at a position facing the wiring boards 1.
以上説明したように、本発明によれば、半導体パッケー
ジおよび入出力ピンを均一に冷却できるため、空気量を
増大させることなく冷却効率を向上させることができる
。しかも、その構造が簡単であるから、コストおよび信
頼性の面で非常に有利である。As described above, according to the present invention, the semiconductor package and the input/output pins can be uniformly cooled, so that the cooling efficiency can be improved without increasing the amount of air. Furthermore, since the structure is simple, it is very advantageous in terms of cost and reliability.
第1図は本発明に係る半導体装置の冷却実装構造を示す
断面図、第2図は第1図のn−n線に沿った断面図、第
3図乃至第6図は本発明の他の実施例を示す断面図、第
7図は従来の半導体装置の冷却実装構造を示す断面図で
ある。
1・・・配線基板、2・・・半導体パッケージ、3・・
・入出力ピン、4・・・半導体チップ、5・・・半田ボ
ール、6.6A・・・孔、7・・・空隙、8,8A・・
・冷却フィン、9・・・ガイド板。FIG. 1 is a sectional view showing a cooling mounting structure of a semiconductor device according to the present invention, FIG. 2 is a sectional view taken along line nn in FIG. 1, and FIGS. FIG. 7 is a cross-sectional view showing an embodiment of the present invention, and FIG. 7 is a cross-sectional view showing a conventional cooling mounting structure for a semiconductor device. 1... Wiring board, 2... Semiconductor package, 3...
・Input/output pin, 4...Semiconductor chip, 5...Solder ball, 6.6A...Hole, 7...Gap, 8,8A...
・Cooling fin, 9...Guide plate.
Claims (9)
力ピンを有する半導体パッケージを、配線基板上に設置
するとともに、前記半導体パッケージと前記配線基板と
の間に空隙を形成し、該空隙内に冷媒を流して前記半導
体チップを冷却する半導体装置の冷却実装構造において
、前記冷媒が流れる孔を、前記半導体パッケージに対向
させて前記配線基板に穿設したことを特徴とする半導体
装置の冷却実装構造。1. A semiconductor package mounted with at least one semiconductor chip and having a large number of input/output pins is installed on a wiring board, a gap is formed between the semiconductor package and the wiring board, and a coolant is flowed into the gap. 1. A cooling mounting structure for a semiconductor device that cools the semiconductor chip using a cooling method, wherein a hole through which the coolant flows is formed in the wiring board so as to face the semiconductor package.
前記半導体パッケージの略中央部に対向した位置に穿設
されていることを特徴とする半導体装置の冷却実装構造
。2. 2. The cooling mounting structure for a semiconductor device according to claim 1, wherein the hole is formed at a position facing substantially the center of the semiconductor package.
複数個穿設され、1つの孔は前記半導体パッケージの略
中央部に対向して、他の孔は前記半導体パッケージの周
縁部に対向してそれぞれ設けられていることを特徴とす
る半導体装置の冷却実装構造。3. In the cooling mounting structure according to claim 1, a plurality of holes are formed, one hole facing a substantially central portion of the semiconductor package, and the other holes facing a peripheral portion of the semiconductor package. A cooling mounting structure for a semiconductor device characterized by being provided with each.
力ピンを有する半導体パッケージを、配線基板上に設置
するとともに、前記半導体パッケージと前記配線基板と
の間に空隙を形成し、該空隙内に冷媒を流して前記半導
体チップを冷却する半導体装置の冷却実装構造において
、前記冷媒が流れる孔を、前記半導体パッケージに対向
させて前記配線基板に穿設するとともに、前記半導体パ
ッケージに冷却フィンを設けたことを特徴とする半導体
装置の冷却実装構造。4. A semiconductor package mounted with at least one semiconductor chip and having a large number of input/output pins is installed on a wiring board, a gap is formed between the semiconductor package and the wiring board, and a coolant is flowed into the gap. A cooling mounting structure for a semiconductor device in which the semiconductor chip is cooled by cooling the semiconductor chip, characterized in that holes through which the coolant flows are formed in the wiring board so as to face the semiconductor package, and cooling fins are provided on the semiconductor package. Cooling mounting structure for semiconductor devices.
力ピンを有する半導体パッケージを、配線基板上に設置
するとともに、前記半導体パッケージと前記配線基板と
の間に空隙を形成し、該空隙内に冷媒を流して前記半導
体チップを冷却する半導体装置の冷却実装構造において
、前記冷媒が流れる孔を、前記半導体パッケージに対向
させて前記配線基板に穿設するとともに、前記半導体パ
ッケージの入出力ピンの基部に冷却フィンを設けたこと
を特徴とする半導体装置の冷却実装構造。5. A semiconductor package mounted with at least one semiconductor chip and having a large number of input/output pins is installed on a wiring board, a gap is formed between the semiconductor package and the wiring board, and a coolant is flowed into the gap. In the cooling mounting structure of the semiconductor device, the hole through which the coolant flows is formed in the wiring board so as to face the semiconductor package, and cooling fins are provided at the base of the input/output pins of the semiconductor package. A cooling mounting structure for a semiconductor device, characterized in that it is provided with a cooling mounting structure for a semiconductor device.
力ピンを有する半導体パッケージを、配線基板上に設置
するとともに、前記半導体パッケージと前記配線基板と
の間に空隙を形成し、該空隙内に冷媒を流して前記半導
体チップを冷却する半導体装置の冷却実装構造において
、前記冷媒が流れる斜めの孔を、前記半導体パッケージ
に対向させて前記配線基板に穿設するとともに、前記孔
へ前記冷媒を導くためのガイド板を形成したことを特徴
とする半導体装置の冷却実装構造。6. A semiconductor package mounted with at least one semiconductor chip and having a large number of input/output pins is installed on a wiring board, a gap is formed between the semiconductor package and the wiring board, and a coolant is flowed into the gap. In the cooling mounting structure for a semiconductor device that cools the semiconductor chip using a cooling device, an oblique hole through which the coolant flows is formed in the wiring board so as to face the semiconductor package, and a guide for guiding the coolant to the hole. A cooling mounting structure for a semiconductor device characterized by forming a plate.
体パッケージが設置された配線基板との間の空隙内に、
冷媒を流すことによって前記半導体チップの冷却を行な
う半導体装置の冷却方法において、前記配線基板に穿設
された孔を介して、前記半導体パッケージの入出力ピン
側に前記冷媒を導入し、この導入された冷媒が前記空隙
内を流れる際に前記半導体チップと冷媒との間で、熱交
換を行なわせることを特徴とする半導体装置の冷却方法
。7. In the gap between the semiconductor package on which the semiconductor chip is mounted and the wiring board on which the semiconductor package is installed,
In a method for cooling a semiconductor device in which the semiconductor chip is cooled by flowing a refrigerant, the refrigerant is introduced to the input/output pin side of the semiconductor package through a hole formed in the wiring board, and the introduced refrigerant is A method for cooling a semiconductor device, characterized in that heat exchange is performed between the semiconductor chip and the refrigerant when the refrigerant flows through the gap.
半導体パッケージが設置された配線基板との間の空隙内
に、冷媒を流すことによって前記半導体チップの冷却を
行なう半導体装置の冷却方法において、前記半導体パッ
ケージに上方より前記冷媒を流して、該冷媒を前記半導
体パッケージの入出力ピン側に導入し、この導入された
冷媒が前記空隙内を流れる際に前記半導体チップと冷媒
との間で、熱交換を行なわせたのち、前記配線基板に穿
設された孔を介して前記冷媒を排出することを特徴とす
る半導体装置の冷却方法。8. In a method for cooling a semiconductor device in which the semiconductor chip is cooled by flowing a refrigerant into a gap between a semiconductor package on which the semiconductor package is mounted and a wiring board on which the semiconductor package is installed, the semiconductor package is cooled from above. The refrigerant is introduced into the input/output pin side of the semiconductor package by flowing the refrigerant, and when the introduced refrigerant flows through the gap, heat exchange is performed between the semiconductor chip and the refrigerant. A method for cooling a semiconductor device, characterized in that the refrigerant is then discharged through a hole formed in the wiring board.
ルーホールとを有する配線基板において、冷却媒体の流
路となる孔が穿設された配線基板。9. A wiring board having at least one conductive layer and through-holes for input/output pins, in which a hole is bored to serve as a flow path for a cooling medium.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63231828A JP2610492B2 (en) | 1988-09-16 | 1988-09-16 | Semiconductor device cooling mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63231828A JP2610492B2 (en) | 1988-09-16 | 1988-09-16 | Semiconductor device cooling mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0281463A true JPH0281463A (en) | 1990-03-22 |
| JP2610492B2 JP2610492B2 (en) | 1997-05-14 |
Family
ID=16929657
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63231828A Expired - Fee Related JP2610492B2 (en) | 1988-09-16 | 1988-09-16 | Semiconductor device cooling mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2610492B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5621597A (en) * | 1991-05-22 | 1997-04-15 | Tdk Corporation | Disc cartridge |
| JP2008205250A (en) * | 2007-02-21 | 2008-09-04 | Fujitsu Ltd | Cold plate and electronic device |
| JP2009260074A (en) * | 2008-04-17 | 2009-11-05 | Seiko Epson Corp | Electronic circuit module, power supply system, and projector |
| JP2009266885A (en) * | 2008-04-22 | 2009-11-12 | Fuji Electric Systems Co Ltd | Cooling device for electronic device with wiring board |
| JP2020051358A (en) * | 2018-09-27 | 2020-04-02 | 株式会社荏原製作所 | Control panel and water supply |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101847166B1 (en) * | 2012-09-28 | 2018-04-09 | 삼성전기주식회사 | Mobile device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56172948U (en) * | 1980-05-21 | 1981-12-21 | ||
| JPS5934156U (en) * | 1982-08-30 | 1984-03-02 | トヨタ自動車株式会社 | Pulley with torsion damper function |
| JPS6027447U (en) * | 1983-07-08 | 1985-02-25 | 富士通株式会社 | radiator |
| JPS6113991U (en) * | 1984-06-29 | 1986-01-27 | 三菱電機株式会社 | Printed wiring board cooling device |
| JPS6242273U (en) * | 1985-09-02 | 1987-03-13 |
-
1988
- 1988-09-16 JP JP63231828A patent/JP2610492B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56172948U (en) * | 1980-05-21 | 1981-12-21 | ||
| JPS5934156U (en) * | 1982-08-30 | 1984-03-02 | トヨタ自動車株式会社 | Pulley with torsion damper function |
| JPS6027447U (en) * | 1983-07-08 | 1985-02-25 | 富士通株式会社 | radiator |
| JPS6113991U (en) * | 1984-06-29 | 1986-01-27 | 三菱電機株式会社 | Printed wiring board cooling device |
| JPS6242273U (en) * | 1985-09-02 | 1987-03-13 |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5621597A (en) * | 1991-05-22 | 1997-04-15 | Tdk Corporation | Disc cartridge |
| JP2008205250A (en) * | 2007-02-21 | 2008-09-04 | Fujitsu Ltd | Cold plate and electronic device |
| JP2009260074A (en) * | 2008-04-17 | 2009-11-05 | Seiko Epson Corp | Electronic circuit module, power supply system, and projector |
| JP2009266885A (en) * | 2008-04-22 | 2009-11-12 | Fuji Electric Systems Co Ltd | Cooling device for electronic device with wiring board |
| JP2020051358A (en) * | 2018-09-27 | 2020-04-02 | 株式会社荏原製作所 | Control panel and water supply |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2610492B2 (en) | 1997-05-14 |
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