JPH0283779A - Instruction execution control method for vector processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a control method for a vector processing device comprising a plurality of pipeline processing mechanisms. The present invention relates to an instruction execution control method for a vector processing device that is suitable for eliminating vector instructions and efficiently processing vector instructions.

[Conventional technology]

When executing a vector instruction in a vector processing device consisting of multiple pipeline processing mechanisms and multiple vector registers, the processing device must determine in advance the pipeline processing mechanisms (also called resources) and vector registers used by the instruction. It is necessary to check whether they are in the "empty" state. If they are not in the "empty" state (this is called a resource conflict or register conflict), execution of the instruction will be delayed. It turns out.

When such a conflict occurs, idle time occurs in resources and registers to which subsequent instructions are allocated, which reduces system performance. As a conventional technique for improving this performance degradation, for example, a technique called "chaining" is known. This technique processes so that even if writing to the vector register by the preceding vector instruction is not completed, the written element can be read by the subsequent instruction. In other words, processing is performed by connecting two pipelines (chain). This chaining can suppress the occurrence of wasted idle time in the pipeline processing mechanism due to register conflicts.

The technology related to chaining is described in "Nikkei Electronics, 1,984.11.19, No. 262.
page to page 264”, “Nikkei Electronics, 198
3.4. , LL, pages 147 to 148" are known.

Furthermore, as a measure to prevent processing device performance from deteriorating in the event of a resource conflict, a method has been proposed in which each resource is provided with a buffer for the next instruction to be executed, and the next instruction is executed immediately after the currently executed instruction is completed.

This technique eliminates wasted time in transmitting and receiving control signals between an instruction activation management circuit and resources, thereby preventing performance degradation of the processing device.

[Problem to be solved by the invention]

However, the prior art does not take into account chaining of write operations to vector registers that are being executed one after another. That is, in the prior art, the issuance or execution of subsequent instructions that write into the vector register is inhibited until the successive writing of the vector register by the preceding instruction is completed, and in cases other than the above,
For example, the issuance or execution of a subsequent instruction is inhibited even when a subsequent instruction continues to issue a register while a preceding instruction is issuing a register, or when a conflict occurs due to shared registers in a vector register peripheral circuit.

As an example, consider the following simple program.

The vector instruction sequence when this is executed by a vector processing device is as follows. Here, VR is a vector register.

In this case, the VRO performs writing using the Load command and S
Although a conflict occurs when reading by the tore instruction, it can be avoided by using the chaining technique described above.

However, the situation changes when considering that the vector instruction is processed by a device with a maximum vector length of 50. In other words, since the vector instruction is vector processing with a vector length of 100, in a device with the vector length of 50, it is necessary to execute the vector instruction twice. The VRO will collide with the command.

In general, conflict avoidance in such cases is not performed because the implementation circuit of the technology equivalent to chaining becomes complicated. As a result, the second execution of the load instruction is
This means that the process will have to wait until the execution of the first Store instruction is completed.

However, in the pipeline processing mechanism, the processing that needs to be suppressed when a conflict occurs as described above is the processing after the write operation to the vector register or the read operation from the hack register, and the At the line stage, processing of the instruction can be executed regardless of conflicts. In other words, in the pipeline processing mechanism, the conventional technology that inputs the subsequent instruction into the pipeline processing mechanism after the preceding instruction completely finishes accessing the vector register wastes idle time for stages unrelated to the conflict. Furthermore, even if the instruction subsequent to the instruction whose issuance was suppressed due to a conflict does not cause a conflict, it may excessively stop subsequent instructions. This has the problem of causing a decline in the performance of the entire processing system.

An object of the present invention is to prevent wasteful idle time from occurring in the execution of a subsequent instruction that causes a conflict with a preceding instruction, and to prevent the conflict 1 from occurring.
An object of the present invention is to provide an instruction execution control system for a vector processing device that can prevent excessive inhibition of the execution of instructions unrelated to - by a relatively simple control mechanism.

[Means to solve the problem]

According to the present invention, the purpose is to provide a circuit for detecting the occurrence of a write conflict in the VR, a circuit for detecting resolution of the conflict, and a circuit for detecting the occurrence of a write conflict between a resource and the VR, which cannot be specified by an instruction. If there is a conflict between one work vector register (hereinafter referred to as WVR) located between When a conflict is detected, depending on whether WVR is empty or not, the instruction in which the conflict was detected is
This is achieved by providing a means for controlling whether to separate and execute the writing into R and the transfer from WVR to VR, or to make the execution wait. Furthermore, the purpose is to return the write destination to the original VR if the conflict is resolved before writing to the WVR begins;
This is achieved by providing a circuit that cancels the second instruction, the transfer from WVR to VR.

[For production]

When the vector processing device attempts to execute a vector instruction, a conflict is detected in which the VR to which the instruction is to write is in use by a preceding instruction, and there are no other conflicts; When it is detected that the WVR is empty, the vector processing device adds an instruction to change the writing destination of the vector instruction to the WVR, issues the instruction to the resource control circuit, and starts executing the instruction. In addition, the vector processing device is
The valid bit of WVR is set to "1" and the VR number to which the instruction is written is held.

As described above, since the writing destination of the vector instruction is changed to WVR, conflicts can be avoided and the vector instruction can be executed. However, in this case, the chaining counter is not counted up. Furthermore, while the valid bit of the WVR is 1'', the write busy status of the write destination VR is set to ``1'', so that subsequent conflict determinations will not be made incorrectly.

When the above-mentioned conflict is resolved, the data written in the WMR is sequentially transferred to the original VR, and at the same time, the chaining counter of the VR is incremented to enable the chaining operation of the subsequent instruction. Ru.

Once the above data transfer from WVR to VR is completed,
The valid bit of WVR is set to "O" and WVR is released.

If the conflict state is resolved after the write destination of the vector instruction is changed to WMR but before writing to WVR is started, the vector processing device issues an instruction to change the write destination of the instruction to WVR. Issue an instruction to cancel 1. At the same time, the valid bit of WVR is set to "O".

As described above, in the present invention, even when a conflict occurs, the amount of available resources can be reduced.

If the vector instruction to be executed is a masked instruction and a conflict similar to the one described above is detected, the vector data is written to WVR, and at the same time, the associated mask value is held in WMR', and the original VR When writing to , it is only necessary to perform the write operation when the mask value is "1", and even if the data is divided into two orders, the result will not be incorrect.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an instruction execution control method for a vector processing device according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a vector processing device to which the present invention is applied, and FIG. 2 is a block diagram showing the configuration of a vector instruction decoding section. In FIG. 1 and FIG. 2, 1 is a scalar processing unit, 2 is a vector instruction execution control device, and 3 is a scalar processing unit.
, 4 is an access instruction processing unit, 5.6 is an arithmetic unit,
9 is a main memory, 20 is a vector instruction decoder, 21 is a vector instruction execution controller, 70 to 77 are vector registers (VR), and 78 is a work vector register (WV).
R), 79 work mask register (WMR)
, 80.81 is a switching circuit, 200 is a vector instruction register, 201 is a pipeline device status display circuit,
202 is a vector register status display circuit, 203 is a work vector register status display circuit, 204 is an execution feasibility determination circuit, 205 is a conflict resolution detection circuit, 213 is a work vector register/registration control counter, and 218 is a decoder.

The vector processing device shown in FIG. 1 includes a scalar processing unit 1 and a vector instruction execution system. It is composed of an fBI device 2, a pipeline processing device consisting of access command processing units 3 and 4, an arithmetic unit 5 and 6, and a plurality of VRs 70-77. In FIG. 1, WVR78 cannot be specified directly depending on the instruction, and WM
R79 holds 1-bit mask data for each element of WVR78.

In the vector I/raw processing apparatus configured as described above,
From the scalar processing unit 1 to the vector instruction execution control device 2
The vector command sent to the vector command control device 2
After the vector instruction decoding unit 20 in the computer decodes, determines whether or not to execute, and allocates resources, the vector instruction execution control unit 21 sends the access instruction processing units 3, 4, VRs 70 to 77, and arithmetic bag of the high line processing device. 25.
6 as execution instruction signals 2a, 2b, and 2c. Note that the mask register 22 in the vector instruction execution control device 2 holds mask information generated by the arithmetic device 5, and this mask information is sent to the pipeline processing device when a masked arithmetic instruction is executed. , is used as a write enable when writing to VR.

In FIG. 2 showing the detailed configuration of the vector instruction decoder 20, the vector instruction register 200 is a register that holds vector instructions sent from the scalar processing unit 1, and the pipeline device status display circuit 201 is a register that holds vector instructions sent from the scalar processing unit 1. This circuit displays the busy state of the instruction processing unit 3.4 and the arithmetic units 5 and 6. In addition, the vector register status display circuit 202 indicates the busy status of VRs 70 to 77.
The workpiece register status display circuit 203 is a WV
This circuit displays the busy state of R78 and the original write destination vector register number. The status display circuit 20
The busy state of 1,202 indicates that the vector instruction execution control unit 2
It is reset by the free signal 21321b from 1.

The vector instructions sent from the scalar processing unit 1 are held in the -.1 hex instruction register 200, and the executable/impossible judgment circuit 204 is operated by the status display circuits 201 to 201 described above.
Arithmetic device 5゜6, VR70-77 and W represented by 203
Based on the busy state of VR7B, it is determined whether this instruction can be executed.

That is, the executable/impossible judgment circuit 204 determines that the above-mentioned instruction can be executed if the devices and registers necessary for executing it are all vacant, and determines that the instruction cannot be executed if the necessary arithmetic device is not vacant. . If it is determined that the instruction cannot be executed, the above-mentioned instruction is held in the vector instruction register 200 until the arithmetic unit 5.6 becomes vacant. In addition, if the necessary adjustment device is empty and only the write destination VR is being read or written and is not empty, and the WVR 713 is empty, the execution possibility determination circuit 204 determines that execution is possible, and sends a signal. 204a to 204C to issue instructions to the vector instruction execution control unit 21. Here, signal 204
A is an execution start instruction signal, a signal 204b is a signal indicating instruction data and the number of processing elements, and a signal 204C is a signal indicating changing the write destination VR to WVR78.

The execution possibility determination circuit 204 issues an instruction to the vector instruction execution control unit 21 as described above, and at the same time outputs the signal 2.
04d, the position of the status display circuit 201, 202 corresponding to the device and register used in the instruction is displayed as busy, and if the instruction includes a write instruction to the WVR78, the work vector register status is The effective bin (V) of the display circuit 203 is set to 1°, and the VRO number and month of the original writing destination are held in the RGN section.

Since the valid bit of the work vector register status display circuit 203 is set to "l", the execution possibility determination circuit 204
Thereafter, it is assumed that the VR with the number held in the RGN section is in the writing operation, and it is possible to correctly determine whether or not subsequent commands can be executed.

-1 R1- The chaining counter is set corresponding to VR70 to 77, and when writing is performed to VR, the rule execution control unit 21 performs "→-1", reads from VR,
Control is performed so that reading 7 does not overtake writing by setting it to "-1" when it is executed.

As described above, when an instruction with a write instruction to the WVR 7B is issued, the signal 21C is given by writing to the WVR 78, the work vector register control counter 213 in the vector instruction decoder 20 is counted up, and the When writing is completed, the signal 21d is applied and the flip-flop 210 is set to 1''.

As described above, if the VR used by the instruction to be executed is being used by the preceding instruction, the data to be written to that VR has been saved to the WVR, and the vector instruction control device 2 It becomes possible to perform the following processing.

After that, the conflict resolution detection circuit 205 monitors the resolution of the conflict, that is, the completion of the read/write re-operation of the VR with the same number as the number held in the RGN section of the work vector register status display circuit 203 for the WVR 78, At this point in time when the end is detected, a pulse signal is sent to AND gates 208 and 209. at this point
If the write start signal 21e to the WVR has already arrived, the flip-flop 206 is 1'', and as a result, the AND circuit 208 outputs the flip-flop 211 indicating permission for transfer from the WVR 78 to the vector register.
is set to “1”. Also, if the write start signal 21141 to WVR78 has not arrived yet, AND
The circuit 209 sets the flip-flop 212 to "1", sends a cancel instruction to the vector instruction execution control unit 21, and changes the write destination to the V with the original VR number.
Instructs to switch to R. At this time, at the same time, OR
The circuit 216 sets its output to 1'' and resets the valid bit of the work vector register status display circuit 203 to “0”.

On the other hand, when the flip-flop 211 is set to "1", if the output of the control counter 213 is 0", that is, if the output of the terminal NZ is "1'", the AND circuit 217 is set to 1'', the read signal 217a for the WVR 7B is sent to the WVR 78, and at the same time, this signal 217a is given to the decoder 218 as an enable signal, and the write signal 218 for the original VR is sent to the WVR 78.
One of the signals a to 218h is sent out, data and mask bits are transferred, and data is originally written to the VR. The aforementioned signals 218a to 218h are simultaneously sent to the execution control unit 21 to count up the chaining counter of the corresponding VR to enable chaining with subsequent instructions.

Further, the write end signal v21d is given from the execution control unit 21 to the WVR 78, and the flip-flop 210 is “
1", if the control counter 213 becomes "0", that is, the output of the terminal Z becomes "1", the AND circuit 21
5 is a flip-flop 2 whose output is "1" and which indicates permission to read the WVR 78 through an OR circuit 214.
11 and the valid bit V of the work vector register status display circuit 203 are reset to "0" through the OR circuit 216, and a signal 215a is sent to the vector instruction execution control section 21 to report the completion of the operation.

In the embodiment of the present invention described above, when a conflict such as a vector register not being free occurs, the instruction at that point is divided into two parts, a write to the WVR and a transfer from the WVR to the VR, and executed. Write the data to the vector register to the work vector register.
・You can evacuate and proceed with the execution of the command,
Vector instructions can be processed efficiently.

In the embodiment of the present invention described above, the WVR has the same configuration as the VR, but the WVR may also be configured by a combination of a data buffer and a pointer.

〔Effect of the invention〕

As explained above, according to the present invention, even if the register used by the instruction to be executed is being used by a preceding instruction, the data to be written to the register is saved to the work vector register. This allows the processing to proceed, thereby preventing the pipeline processing mechanism from wasting idle time and efficiently processing vector instructions.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a vector processing device to which the present invention is applied, and FIG. 2 is a block diagram showing the configuration of a vector instruction decoding section. 1... Scalar processing unit I, 2...
...Vector instruction control device, 3, 4...
...Access command processing unit, 5.6...
... Arithmetic unit, 9... Main storage device,
20...Vector instruction decoding section, 21...
......Vector instruction execution control unit, 70-77.
・・・・・・Vector register (VR), 78...
・・・・・・Work vector register (WVR),
79... Work mask register (WMR
), 80.81...Switching circuit, 200...Vector instruction register, 2
01...Pipeline device status display circuit, 202...Vector register status display circuit, 203...Work vector register status display circuit, 204......Vector execution feasibility determination circuit, 205...Conflict resolution detection circuit, 213...Work vector register control counter, 218...・・・・・・・・・
decoder. 79: 7-f7z 7reister (WMR)

Claims (1)

[Claims] 1. A vector register that holds data of multiple elements;
A vector processing device that includes a plurality of pipeline processing mechanisms that sequentially process multiple elements of data in the vector register, and that assigns and processes individual vector instructions to each pipeline processing mechanism, In addition to the vector register specified by the instruction, a work vector register that cannot be directly specified by the instruction and a vector register specified by the instruction assigned to each pipeline or a write path to the vector register precedes. and a mechanism for detecting a conflict state in which the instruction is being used by an instruction, and when a conflict state is detected, the instruction to be assigned to the pipeline is
An instruction execution control method for a vector processing device, characterized in that execution is divided into two parts: writing to the work vector register and transferring from the work vector register to the vector register. 2. Hold the instruction that causes the transfer from the work vector register to the vector register until the instruction becomes executable, allow subsequent instructions to overtake and execute, and start writing to the work vector register. If the conflict is resolved beforehand, the writing destination is immediately changed to the original vector register, and the instruction for causing the transfer from the work vector register to the vector register is canceled. An instruction execution control method for a vector processing device according to item 1. 3. Claims 1 or 2 further comprising a mask register that holds mask information corresponding to each vector element of the work vector register, making it possible to execute masked vector instructions. Instruction execution control method of the vector processing device described.