JPH02842U - - Google Patents
Info
- Publication number
- JPH02842U JPH02842U JP7743788U JP7743788U JPH02842U JP H02842 U JPH02842 U JP H02842U JP 7743788 U JP7743788 U JP 7743788U JP 7743788 U JP7743788 U JP 7743788U JP H02842 U JPH02842 U JP H02842U
- Authority
- JP
- Japan
- Prior art keywords
- low frequency
- reference clock
- clock signal
- amplification
- multiplier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003321 amplification Effects 0.000 claims description 5
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 5
- 238000001514 detection method Methods 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 1
Landscapes
- Circuits Of Receivers In General (AREA)
Description
第１図は本考案の一実施例の受信機３１の電気
的構成を示すブロツク図、第２図および第３図は
動作を説明するための波形図、第４図は本考案の
他の実施例の受信機８１の電気的構成を示すブロ
ツク図、第５図は振幅変調信号をダイレクト検波
するための基本的な受信機１の電気的構成を示す
ブロツク図、第６図は従来技術の受信機１ａの電
気的構成を示すブロツク図である。
３１，８１…受信機、３２…アンテナ、３３…
高周波増幅回路、３４…直交変換回路、３７，３
８，４１，４２，４６…乗算器、３９，４０，５
６…ＬＰＦ、４３…加算器、４４…演算回路、４
７…増幅器、４８…電力増幅器、４９…スピーカ
、５０…同調制御回路、５９…ゲイン調整回路、
６１，７１，８４，８５…切換スイツチ、６５…
増幅回路、６８，８８…クロツク発生回路、８２
…アナログ／デジタル変換器、８３…デジタル信
号処理回路、８９…デジタル／アナログ変換器。
FIG. 1 is a block diagram showing the electrical configuration of a receiver 31 according to an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams for explaining the operation, and FIG. 4 is a diagram showing another embodiment of the present invention. A block diagram showing the electrical configuration of an example receiver 81, FIG. 5 is a block diagram showing the electrical configuration of the basic receiver 1 for direct detection of an amplitude modulated signal, and FIG. 6 is a conventional reception technique. FIG. 2 is a block diagram showing the electrical configuration of the machine 1a. 31, 81...Receiver, 32...Antenna, 33...
High frequency amplifier circuit, 34... Orthogonal conversion circuit, 37, 3
8, 41, 42, 46...multiplier, 39, 40, 5
6...LPF, 43...Adder, 44... Arithmetic circuit, 4
7... Amplifier, 48... Power amplifier, 49... Speaker, 50... Tuning control circuit, 59... Gain adjustment circuit,
61, 71, 84, 85...changeover switch, 65...
Amplification circuit, 68, 88... Clock generation circuit, 82
...Analog/digital converter, 83...Digital signal processing circuit, 89...Digital/analog converter.
Claims (1)
する第１乗算器と、 前記第１基準クロツク信号に対して位相の異な
る第２基準クロツク信号と前記受信信号とを乗算
する第２乗算器と、 前記第１および第２乗算器の後段にそれぞれ設
けられる第１および第２低域波手段と、 前記第１および第２低域波手段の後段に設け
られる単一の増幅手段と、 増幅手段を前記第１または第２低域波手段に
選択的に接続する選択手段と、 前記増幅手段の後段に設けられ、検波出力を発
生する処理手段とを含むことを特徴とする受信装
置。 (2) 前記増幅手段の後段にアナログ／デジタル
変換手段を設け、その出力をデジタル信号処理手
段に入力して検波処理を行うようにしたことを特
徴とする実用新案登録請求の範囲第１項記載の受
信装置。[Claims for Utility Model Registration] (1) A first multiplier that multiplies a first reference clock signal and a received signal; a second reference clock signal that has a different phase with respect to the first reference clock signal and the received signal; a second multiplier that multiplies the first and second low frequency means; first and second low frequency means respectively provided after the first and second multipliers; and first and second low frequency means provided after the first and second multipliers. comprising: a single amplification means; a selection means for selectively connecting the amplification means to the first or second low frequency means; and a processing means provided after the amplification means and generating a detection output. A receiving device characterized by: (2) Claim 1 of the Utility Model Registration Claim characterized in that an analog/digital conversion means is provided after the amplification means, and the output thereof is input to a digital signal processing means to perform detection processing. receiving device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7743788U JPH0520023Y2 (en) | 1988-06-11 | 1988-06-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7743788U JPH0520023Y2 (en) | 1988-06-11 | 1988-06-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02842U true JPH02842U (en) | 1990-01-05 |
| JPH0520023Y2 JPH0520023Y2 (en) | 1993-05-26 |
Family
ID=31302421
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7743788U Expired - Lifetime JPH0520023Y2 (en) | 1988-06-11 | 1988-06-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0520023Y2 (en) |
-
1988
- 1988-06-11 JP JP7743788U patent/JPH0520023Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0520023Y2 (en) | 1993-05-26 |
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