JPH0284434U - - Google Patents
Info
- Publication number
- JPH0284434U JPH0284434U JP16312688U JP16312688U JPH0284434U JP H0284434 U JPH0284434 U JP H0284434U JP 16312688 U JP16312688 U JP 16312688U JP 16312688 U JP16312688 U JP 16312688U JP H0284434 U JPH0284434 U JP H0284434U
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- transistor
- gate
- emitter
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Electronic Switches (AREA)
Description
第１図は本考案による第１の実施例を示す回路
構成図、第２図、第３図は本考案による第２、第
３の実施例を示す回路構成図、第４図は従来にお
けるタイマ回路の回路図である。
１…直流電源、２……負荷、３……ＭＯＳ Ｆ
ＥＴ、４……コンデンサ、５……開閉器、６，７
，８，９，１０……抵抗、１１，１２……トラン
ジスタ、１３……ダイオード、１４……定電圧ダ
イオード。
Fig. 1 is a circuit diagram showing a first embodiment of the present invention, Figs. 2 and 3 are circuit diagrams showing second and third embodiments of the invention, and Fig. 4 is a conventional timer. It is a circuit diagram of a circuit. 1...DC power supply, 2...Load, 3...MOS F
ET, 4... Capacitor, 5... Switch, 6, 7
, 8, 9, 10... Resistor, 11, 12... Transistor, 13... Diode, 14... Constant voltage diode.
Claims (1)
Ｔと、該ＭＯＳ ＦＥＴのゲートソース間に接続
したコンデンサと第１の抵抗の並列回路と、ベー
スを第２の抵抗を介して前記ＭＯＳ ＦＥＴのド
レインに接続しコレクタをゲートにエミツタをソ
ースに接続した第１のトランジスタと、該第１の
トランジスタのベースエミツタ間にそれぞれコレ
クタエミツタを接続しベースを第３の抵抗と開閉
器を介して前記直流電源に接続した第２のトラン
ジスタと、前記開閉器と第３の抵抗の接続点に一
端を接続した第４の抵抗の他端にアノードを接続
しカソードを前記ＭＯＳ ＦＥＴのゲートに接続
したダイオードとを有することを特徴とするタイ
マ回路。 MOS FE connected in series with load to DC power supply
T, a parallel circuit of a capacitor and a first resistor connected between the gate and source of the MOS FET, a base connected to the drain of the MOS FET via a second resistor, a collector connected to the gate, and an emitter connected to the source. a first transistor having a collector-emitter connected between the base and emitter of the first transistor, and a second transistor having a base connected to the DC power supply via a third resistor and a switch; and a diode having one end connected to the connection point of the third resistor, an anode connected to the other end of the fourth resistor, and a cathode connected to the gate of the MOS FET.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16312688U JPH0284434U (en) | 1988-12-16 | 1988-12-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16312688U JPH0284434U (en) | 1988-12-16 | 1988-12-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0284434U true JPH0284434U (en) | 1990-06-29 |
Family
ID=31447571
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16312688U Pending JPH0284434U (en) | 1988-12-16 | 1988-12-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0284434U (en) |
-
1988
- 1988-12-16 JP JP16312688U patent/JPH0284434U/ja active Pending