JPH0284835A - Inter-cross polarization interference compensator - Google Patents

Abstract

PURPOSE:To compensate delay difference between a main polarization and a cross polarization being generated due to fading on a transmission path, etc., adaptively, to prevent inter-cross polarization interference compensation capacity from being lowered, and to operate a device at code speed by providing a compensation signal generation circuit, etc. CONSTITUTION:A signal of cross polarization is inputted to a cross polarization demodulation circuit 41, and identification and demodulation are applied on the signal by the circuit 41, and a clock generation circuit 42 generates a clock to be used in the decision of the timing of signal identification at the circuit 41. Also, a phase control circuit 45 judges the direction of the phase of a timing clock to obtain the optimum interference effect by adjusting in either the direction to lead or lag based on the tap coefficient Cn of the compensation signal generation circuit 43. A compensation signal is generated from the compensation signal generation circuit 43 based on a demodulation signal whose identification timing can be set at the optimum level by adjusting the phase of the timing clock supplied to the circuit 41 based on a judged result, and an interference signal in the main polarization can be suppressed by using the compensation signal. In such a way, it is possible to prevent the inter-cross polarization interference compensation capacity from being lowered, and to operate the device at the code speed.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Conventional technology (Figures 7 and 8) Problems to be solved by the invention (Figures 9 and 1O) Solving the problems Means for (Figure 1) Working Examples (Figures 2 and 3) Modifications (Figures 4 and 5) Effects of the Invention Compensation in which a compensation signal for canceling an interference signal is generated using a transversal filter signal generation circuit.

A synthesis circuit uses the compensation signal of the compensation signal generation circuit to remove the interference signal in the main polarization, and a clock generation circuit uses the clock generation circuit to maximize the interference signal suppression effect based on the tap coefficient of the compensation signal generation circuit. and a phase control circuit for controlling the phase.

〔overview〕

Regarding a cross-polarization interference compensation device in a cross-polarization shared transmission system receiver.

An interference system that adaptively compensates for the delay difference between the main polarization and the cross-polarization caused by fading in the transmission path, prevents the cross-polarization interference compensation ability from decreasing, and operates at the code speed. The purpose is to provide a compensation device.

a cross-polarization demodulation circuit that identifies and demodulates cross-polarization signals;
Based on a clock generation circuit that generates a clock used to determine the timing of signal identification in a cross-polarization demodulation circuit and a demodulated signal of the cross-polarization demodulation circuit [Industrial Application Field] The present invention is based on a cross-polarization shared transmission system. The present invention relates to a cross-polarization interference compensation device in a receiver.

[Conventional technology]

In order to improve the efficiency of dual frequency use in digital wireless communication systems, multi-leveling is being promoted, and currently 256QA
The M method has even been introduced to test lines for practical use. Along with this multi-value.

Attempts have also been made to simply double the transmission capacity in the same frequency band compared to the conventional single-polarization transmission system by sharing the polarization planes of main polarization and cross-polarization.

The communication system based on this cross-polarization shared transmission method is shown in Figure 7. In figure 0, 20 and 30 are transmitters for vertical polarization ■ and horizontal polarization H, respectively, and 21 to 27 are for vertical polarization V side. The receiving devices 31 to 37 are horizontally polarized H side receiving devices.

21.31 is a receiving section, and 22.32 is a demodulation circuit.

23.33 is a discriminator that identifies main polarization signals; 24.3
4 is a discriminator that discriminates signals on the cross-polarized side.

25.35 is a transversal equalizer that equalizes the demodulated signal of the main polarization, 26.36 is a compensation signal generation circuit that generates a compensation signal for removing the interference signal in the main polarization, 27
．． 37 is a combining circuit that removes the interference signal by subtracting the compensation signal from the main polarization. Here, the compensation signal generation circuits 26 and 36 generally use transversal filters.

This system uses vertically polarized waves ■ and horizontally polarized waves H on a wireless transmission path.
When interference occurs between the two polarized waves and one polarized wave (main polarized wave) leaks into the other polarized wave (cross polarized wave) as an interference wave, in the receiving device on the main polarized side.

A compensation signal having a frequency characteristic opposite to that of the interference signal in the main polarization is created by waveform-shaping the cross-polarized waves, and this compensation signal cancels the interference signal to compensate for the interference between the cross-polarized waves. A cross-polarization interference compensator is used to suppress this interference between polarizations.

FIG. 8 shows a cross-polarization interference compensation device in the case where the vertical polarization V is the main polarization. As shown in FIG. 8, the discriminators 23 and 24 are composed of A/D converters, A/
As the timing clock for the D converters 23 and 24, the clock cycle of the data signal extracted and reproduced from the demodulation circuit 22 in the clock reproduction circuit 28 is used.

[Problem to be solved by the invention]

In a conventional cross-polarization interference compensation device, the compensation ability is degraded if there is a delay difference between the interference signal included in the main polarization and the compensation signal for interference wave compensation created on the receiving side. This delay difference occurs based on the propagation distance difference between the main polarization and the cross polarization due to multipath fading in the wireless transmission path.

The above-mentioned decrease in compensation ability can be explained as follows. FIG. 9 shows the phase relationship between the main polarization and the cross-polarization just before cross-polarization interference occurs in the transmission path. Here, the interference wave to the main polarization is naturally in the same phase as the cross polarization.

On the other hand, when the main polarized wave and the cross-polarized wave are received by the receiving device in a state where there is a propagation path difference between them in the transmission path 5, the phase relationship between the main polarized wave and the cross-polarized wave is shown in FIG. 10, for example. As shown in FIG. 9, the phase of the cross-polarized waves is delayed by τ compared to the phase relationship shown in FIG. In the receiver's demodulation circuit discriminator*
Both the main polarization and the cross polarization are identified at time tl, '2.

Here, what is the suppression of the interference signal leaking into the main polarization?

This is done by subtracting from the main polarization a compensation signal that has been waveform-shaped with cross-polarized waves so that the characteristics are equal to those of this interference signal. However, since the compensation signal is generated based on the cross-polarized wave identified with a phase different from the phase of the interference signal in the main polarization, the error between the compensation signal and the interference signal becomes large, and therefore the compensation ability decreases. decreases.

When there is a propagation delay difference between the main polarization and the cross polarization in this way, the conventional method is as shown in FIG. 8, for example.

By matching the delay differences between A and A' on the input side of the discriminators 23 and 24, the phases of the interference signal and the compensation signal included on the main polarization side are set to be in an optimal state.

However, if a random delay difference occurs between the main polarization and the cross-polarization due to multipath fading in the transmission path, this cannot be compensated for, and the cross-polarization quantum 8-interference compensation device A significant deterioration in performance cannot be avoided.

As a countermeasure for this, the
Instead of r space type transversal filter,
The apparatus may be constructed using a fractional space type transversal filter that is not affected by delay differences, for example, a T/2 space type tosi transversal filter.

However, in this case, the operating clock of the discriminator is twice that of the T-space type, and the A/D converter used is required to have twice the operating speed.

Therefore, it is an object of the present invention to adaptively compensate for the delay difference between the main polarization and the cross-polarization caused by fading in the transmission path, to prevent the deterioration of the cross-polarization interference compensation ability, and to The object of the present invention is to provide an interference compensation device that operates at high speed.

[Means to solve the problem]

FIG. 1 is a principle block diagram according to the present invention.

The cross-polarization interference compensation device according to the present invention includes a cross-polarization demodulation circuit 41 that identifies and demodulates a cross-polarization signal, and a clock that generates a clock used to determine the timing of signal identification in the cross-polarization demodulation circuit 41. Generation circuit 42 and cross-polarized wave 1
A compensation signal generation circuit 43 generates a compensation signal using a transversal filter to cancel an interference signal based on the demodulated signal of the 1!1 circuit 41, and a compensation signal generation circuit 43 generates a compensation signal in the main polarization using the compensation signal of the compensation signal generation circuit 43. Synthesis circuit 4 that removes
4, and a black signal generation circuit 42 so as to increase the interference signal suppression effect based on the tap coefficient of the compensation signal generation circuit 43.
and a phase control circuit 45 for controlling the phase of the clock.

[Effect]

The phase control circuit 45 determines from the tap coefficients of the compensation signal generation circuit 43 which direction it is best to adjust the phase of the timing clock, leading or delaying, in order to obtain the optimal interference effect, and adjusts the cross bias. The phase of the timing clock supplied to the wave demodulation circuit 41 is adjusted in that direction. A compensation signal is generated in the compensation signal generation circuit 43 based on the demodulated signal whose identification timing is optimized in this way, and this is used to suppress the interference signal in the main polarization.

〔Example〕

The present invention will be described in detail below with reference to two drawings. FIG. 2 is a block diagram showing a cross-polarization interference compensation device as an embodiment of the present invention. This embodiment device uses 64-value QAM
Although the present invention is applied to a system receiver, only the I channel circuit is shown in the drawing for the sake of simplicity. Also, interference between the I channel and Q channel is ignored here.

In FIG. 2, the received main polarized wave is demodulated by a demodulation circuit 1, and the signal level of the output signal is discriminated by a discriminator 2 consisting of an A/D converter. In this example, 64-value QAM
Therefore, the number of levels (multilevel number) of the demodulated signal of the main polarization is 8 and 2. From the discriminator 2, 3 bits (Pl, P2.P
In addition to the data signal (3), a 2-bit (P4.Ps) error signal is added, and a total of 5 pin signals are output.

After the distortion of the output signal from the discriminator 2 is equalized by an equalizer 3, the interference wave component is removed by a subtracter 9.

It is output as output data Do.

On the other hand, the cross-polarized waves are demodulated by a demodulation circuit 6 and input to a discriminator 7 consisting of an A/D converter, where the level is discriminated, and then input to a compensation signal generation circuit 8 consisting of a T-space type transversal filter. Ru. Compensation signal generation circuit 8 generates a compensation signal for canceling the interference wave signal in the main polarization based on the output signal of discriminator 7 and sends it to subtractor 9 .

A schematic configuration example of the compensation signal generating circuit 8 is shown in FIG. 3, and is composed of a 5-tap one-dimensional T-space type transversal filter, and four cascade-controlled delay units 81. 814 and weighting for multiplying their inputs and outputs by tap coefficients C-2 to C2 are configured to include a circuit and a synthesizer 83 that adds the outputs thereof to generate a compensation signal yK. Here, the tap coefficient co is the center tap To
is the coefficient of

Reference numeral 4 denotes a clock regeneration circuit which extracts and regenerates a clock having the period of the information symbol from the demodulated signal of the main polarization. This clock is supplied to the discriminator 2 and used as a timing clock for signal discrimination, and is also supplied to the discriminator 7 after being shifted by the phase amount formed by the phase shifter 5, and is used as a timing clock for signal discrimination. It is said that

The phase amount of the phase shifter 5 is adaptively controlled by a control circuit 10. The control circuit 10 includes comparators 11, 12, 15, AND gates 13, 14, and an up/down counter 16.
It consists of:

The comparator 11 receives the output data D from the subtracter 9.

The error signal εl (Pa, Ps of the lower two pinpoints) is input, and the comparator 11 converts it to a predetermined threshold value TH.
If the error signal t1 is larger than 1, "1" is output to the AND gate 13, and if it is smaller, "0" is output to the AND gate 13.

Further, a compensation signal yg is input to the comparator 12, and this comparator 12 also compares the compensation signal y with a predetermined threshold value TH2, and if the compensation signal y is large, "l" is input.
If it is smaller, 0'' is output to the AND gate 13.

AND gate 14 has AND gate 113 connected to one input terminal.
An output signal from the up/down counter 16 is inputted to the other input terminal, and a clock CL having a constant period is inputted to the other input terminal, and the output signal is inputted to the clock input terminal of the up/down counter 16.

The comparator 15 includes taps T-1 and T before and after the center tap To of the transversal filter in the compensation signal generating circuit 8.
The coefficients C-1 and 01 of
Output to the count up and count down mode switching control terminal. The counter 16 outputs the count value to the phase shifter 5 as a phase control amount θd.

The operation of the example device will be described below. The interference wave signal included in the main polarization is half canceled by the compensation signal generated by the compensation signal generation circuit 8, thereby performing interference compensation. At this time, it is necessary to have a small error between the interference wave signal and the compensation signal in order to increase the interference compensation effect, and to reduce the error, it is necessary to shift the phase of the cross-polarized signal identification timing clock in the discriminator 7. It is necessary to make appropriate adjustments using the device 5.

This phase adjustment method is performed as follows.

When waveform equalization is performed using a transversal filter, whether or not waveform distortion has occurred can be determined by monitoring tap coefficients C-2 to C2. Distortion is winimuse
Whether this is due to fade (minimum phase shifting fading) or non minimum fade (non minimum phase shifting fading) can be determined by knowing which tap coefficients before or after the center tap are controlled to a greater extent.

Therefore, the coefficients C and C of the taps before and after the center tap of the transversal filter in the compensation signal generation circuit 8
By comparing the magnitude of 1.

It is possible to determine whether the amount of intersymbol interference on the leading side or the amount of intersymbol interference on the lagging side is large, and thereby it can be determined whether the phase of the identification timing clock is ahead or behind the optimal one.

This determination is made in the comparator 15, and as a result, if the phase of the timing clock is to be advanced, an output signal is sent to set the mode of the counter 16 to the up-count mode, whereas if the phase of the timing clock is to be delayed by one phase, the counter 16 is sent to the up-count mode. Sends an output signal so that it is in down count mode.

The counter 16 amplifies or counts down the counting clock CLK from the AND gate 14 based on the output signal from the comparator 15.

The resulting count value is sent to the phase shifter 5 as a phase amount control signal θd. As a result, the phase shifter 5 shifts the clock from the clock recovery circuit 4 by θd.

As a result of interference compensation, the error signal ε2 of the output data D,
is smaller than a predetermined value TH1, or if the compensation signal yK is smaller than a predetermined value TH2 (ie, the interference is small), it is not necessary to perform phase control of the phase shifter 5. The comparators 11, 12 then determine these conditions, and the AND gate 13 closes the AND gate 14 to cut off the clock CL supplied to the counter 16, thereby stopping the phase control operation.

Various modifications are possible in implementing the present invention. FIG. 0g44 is a block diagram showing such a modification, and shows the configuration of a control circuit portion that sends the phase control amount θd to the phase shifter. A compensation signal yg and an error signal ε2 are input to this control circuit.

It consists of a coefficient calculation circuit 50 that calculates the tap coefficients C-+, Co, and C of the transversal filter in the compensation signal generation circuit 8 from these, and a phase amount calculation circuit 60 that calculates the phase control amount θd from these coefficients. .

The coefficient calculation circuit 50 is a known circuit having the same configuration as the transversal filter coefficient control circuit in the compensation signal generation circuit 8, and can also be used in common with the transversal filter coefficient control circuit. This coefficient calculating circuit 50 includes a flip-flop 51. Exclusive OR circuit 5
2-54. It is configured to include up/down counters 55-57.

Its operation is performed by a flip-flop 51 and exclusive OR circuits 52 to 53, each with a central tap T.

The correlation between the taps 'r-1 and 'r before and after it is taken, and the counters 55 to 57 integrate the correlation, so that the counters 55 to 57
Tap coefficients C-1°Go, C, are obtained at the outputs of 57, respectively.

The phase amount calculation circuit 60 includes an exclusive OR circuit 61. to which the coefficients C-+ and C are input. Exclusive OR circuit 62 to which the coefficients co and 01 are input. An exclusive OR circuit 63 to which the output signals of the exclusive OR circuit 61 and 6''1 are input.Up/down counter 64.The output signal of the exclusive OR circuit 63 is input to one side and the counting clock CLK is input to the other side. The counter 64 includes an AND circuit 65 to which the counter 64 is inputted.
The up/down mode is set by the output signal of the exclusive OR circuit 61.

The operation of this modified device will be explained below.

If the times of the interference wave and the compensation wave match, Fig. 5 (A
), the transversal filter in the compensation signal generating circuit 8 has a center tap T.

only is output. On the other hand, when the compensation wave has a time delay with respect to the interference wave as shown in 1ffi (B), taps T-1 and T1 before and after the center tap To
outputs a signal with opposite polarity. Therefore.

Using this, the center tap To and the control signal in the direction (
tap coefficient) on the side of the tap that is outputting.

By shifting the phase of the clock supplied to the discriminator 7 using the phase shifter 5, the optimum discrimination timing can be found.

This 'HA@ direction determination is performed by exclusive OR circuits 61 to 63.
When the output signals of the exclusive OR circuits 61 and 62 are the same, the AND circuit 65 is closed and the counter 64 is
is stopped, and when the output signal of the exclusive OR circuit 61 is 61'', the counter 64 is set to count up mode, and the
Set to countdown mode at 0°. The output signal of the counter 64 is then used as the clock phase control amount θd and sent to the phase shifter 5.

The above embodiments are based on transversal filters with a one-dimensional configuration, but the transversal filter is not limited to this. The present invention can be implemented using a transversal filter of the configuration. FIG. 6 is a diagram showing the configuration of the compensation signal generation circuit portion in the case of such a two-dimensional configuration. Four transversal filter sections are provided in the compensation signal generation circuit so as to also compensate for interference between the channel and the Q channel.

Further, in the above-described embodiment, the interference wave component is canceled by the compensation signal in the baseband band, but the present invention is not limited to this, and a configuration in which the interference wave component is canceled in the IF band is also possible.

Furthermore, it is clear that the present invention is applicable to either analog or digital circuits.

〔Effect of the invention〕

According to the present invention, even if the delay difference between the main polarization and the cross-polarization changes randomly due to fading, etc., this is compensated for by adaptively controlling the signal identification timing on the cross-polarization side, and the delay difference is absorbed. This can prevent the ability to compensate for cross-polarized waves from decreasing due to the occurrence of a delay difference between polarized waves. Furthermore, the transversal filter used to generate the compensation signal may be of the T-space type, and as a result, when the code speed is increased compared to the flag-silanal-space type, restrictions on the upper limit of the frequency of the elements used can be relaxed. be able to.

[Brief explanation of the drawing]

FIG. 1 is a principle block diagram according to the present invention. FIG. 2 is a block diagram showing a cross-polarization interference compensation device as an embodiment of the present invention. FIG. 3 is a block diagram showing a configuration example of the transversal filter section of the compensation signal generation circuit in the embodiment device. FIG. 4 is a block diagram showing the configuration of a modified example of the present invention. FIG. 5 is a diagram for explaining the operation of the modified example device. FIG. 6 is a block diagram of a modification in which the present invention is applied to a two-dimensional cross-polarization interference compensation device. FIG. 7 is a block diagram showing a schematic configuration example of a conventional polarization sharing system. FIG. 8 is a block diagram showing a conventional cross-polarization interference compensation device; FIG. 9 and FIG. 1O are diagrams illustrating the cause of a decrease in interference compensation ability due to a delay difference between polarized waves. In fig. 1, 6. 22. 32... Demodulation circuit 2.7.2
3, 24, 33, 34 - Discriminator 3.25.36 - Equalizer 28 - Clock recovery circuit Phase shifter 26.36 - Compensation signal generation circuit Subtractor control circuit 12, i5 - M - Comparator 14.65...and gate 55-57. e+4-・-up/down counter 8゜11゜13゜16゜flip flop 52-54.61-63-exclusive OR circuit/j-thigh e
Monthly scraps, physical block diagram supplementary name J5 1 circuit 4 evaporated metal 11 3rd diagram 11 'Gravity 4 Theory Sun Moon Diagram Figure 5 Orthogonal 2 Stars Original 1 (Board Yoro Shikata Kaba 11 Figure 6 Configuration Example of 4S Wave Common System Figure 7 Figure 8 Correlation at the time of interference Figure 9 Correlation at receiver input Figure 10

Claims (1)

[Claims] 1. A cross-polarization interference compensation device that suppresses the influence of interference waves in the main polarization leaking from cross-polarization in a cross-polarization shared transmission system receiver, which a cross-polarization demodulation circuit (41) that identifies and demodulates the signal of the cross-polarization demodulation circuit; a clock generation circuit (42) that generates a clock used to determine the timing of signal identification in the cross-polarization demodulation circuit; and a demodulation of the cross-polarization demodulation circuit. a compensation signal generation circuit (43) that uses a transversal filter to generate a compensation signal that cancels the interference signal based on the signal; a synthesis circuit that uses the compensation signal of the compensation signal generation circuit to eliminate the interference signal in the main polarization; (44), and a phase control circuit (45) that controls the phase of the clock of the clock generation circuit so as to increase the suppression effect of the interference signal based on the tap coefficient of the compensation signal generation circuit. Inter-polarization interference compensation device. 2. The control circuit is configured to control the phase amount of the clock generation circuit based on the magnitude relationship between the leading side intersymbol interference amount and the lagging side intersymbol interference amount determined from the tap coefficients of the compensation wave generation circuit. 2. The cross-polarization interference compensator according to item 1. 3. The control circuit is configured to change the control phase amount of the clock generation circuit to the tap having the same polarity as the tap coefficient of the main tap among the taps before and after the main tap of the compensation wave generation circuit. The cross-polarization interference compensation device according to claim 1.